FEDR26V51252R-002-02
Issue Date: Oct. 01, 2008
MR26V51252R
32M–Word
16–Bit or 64M–Word
8–Bit
Page Mode
P2ROM
PIN CONFIGURATION (TOP VIEW)
FEATURES
32Mx16 or 64Mx8-bit
electrically switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6 V power supply
·Random Access time
105 ns MAX
·Page Access time
25 ns MAX
· Operating current
50 mA MAX
· Standby current
4 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR26V51252R-xxxTA
56-pin plastic TSOP (P-TSOP(1)56-1420-0.50-K-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits over
the other non-volatile technologies, which include the
following;
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
TSOP
(type1)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A24
NC
A16
BYTE#
Vss
D15/A-1
D7
D14
D6
D13
D5
D12
D4
Vcc
D11
D3
D10
D2
D9
D1
D8
D0
OE#
Vss
CE#
A0
NC
Vcc
·
Short lead time,
since the P2ROM is programmed at the final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive
lead-time and minimize liability as a custom product.
·
No mask charge,
since P2ROMs do not utilize a custom mask for storing customer code, no mask charges
apply.
·
No additional programming charge,
unlike Flash and OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput.
The cost is included in the unit price.
·
Custom Marking
is available at no additional charge.
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FEDR26V51252R-002-02
MR26V51252R / P2ROM
BLOCK DIAGRAM
A-1
× 8/× 16 Switch
CE#
CE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
OE#
OE
BYTE#
Row Decoder
Memory Cell Matrix
32M × 16-Bit or 64M × 8-Bit
Address Buffer
Column Decoder
Multiplexer & Sense Amp.
Output Buffer
D0
D1
D2
D3
D4
D5
D6
D7
D8
D10
D9
D12
D14
D15
D11
D13
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A24
D0 to D14
CE#
OE#
BYTE#
V
CC
V
SS
NC
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
No connect
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FEDR26V51252R-002-02
MR26V51252R / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
Output disable
Standby
CE#
L
L
L
H
OE#
L
L
H
BYTE#
H
L
H
L
H
L
3.3 V
D
OUT
Hi–Z
Hi–Z
V
CC
D0 to D7
D8 to D15
D
OUT
Hi–Z
A-1
L/H
:
Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Output short circuit current
Power dissipation per package
Symbol
Ta
T
STG
V
I
V
O
V
CC
I
OS
P
D
Condition
—
Value
0 to 70
–55 to 125
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–0.5 to 5
10
1.0
Unit
C
C
V
V
V
mA
W
relative to V
SS
—
Ta=25C
RECOMMENDED OPERATING CONDITIONS
Parameter
V
CC
power supply voltage
Input “H” level
Input “L” level
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
= 3.0 to 3.6 V
Min.
3.0
2.2
–0.5
Typ.
—
—
—
(Ta = 0 to 70C)
Max.
Unit
3.6
V
V
CC
+0.5
V
0.6
V
Voltage is relative to V
SS
.
: V
CC
+1.5V(Max.) when pulse width of overshoot is less than 10ns.
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input
BYTE#
Output
D15/A-1
Symbol
C
IN1
C
IN2
C
OUT1
C
OUT2
Condition
V
I
= 0 V
V
O
= 0 V
Min.
—
—
—
—
(V
CC
= 3.3 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
10
—
200
pF
—
20
—
20
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FEDR26V51252R-002-02
MR26V51252R / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
I
LI
I
LO
I
CCSC
I
CCST
I
CCA1
V
IH
V
IL
V
OH
V
OL
Condition
V
I
= 0 to V
CC
V
O
= 0 to V
CC
CE# = Add.=V
CC
CE# = Add.=V
IH
CE# = V
IL
OE# = V
IH
tc = 200 ns
Min.
—
—
—
—
—
2.2
–0.5
2.4
—
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70C)
Typ.
Max.
Unit
—
10
A
—
10
A
—
4
mA
—
4
mA
—
—
—
—
—
50
V
CC
+0.5
0.6
—
0.4
mA
V
V
V
V
—
—
I
OH
= –2 mA
I
OL
= 2 mA
Voltage is relative to V
SS
.
: V
CC
+1.5V(Max.) when pulse width of overshoot is less than 10ns.
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
Parameter
Address cycle time
Address access time
Page cycle time
Page access time
CE# access time
OE# access time
Output disable time
Output hold time
Symbol
t
C
t
ACC
t
PC
t
PAC
t
CE
t
OE
t
CHZ
t
OHZ
t
OH
Condition
—
—
—
CE# = OE# = V
IL
OE# = V
IL
CE# = V
IL
OE# = V
IL
CE# = V
IL
CE# = OE# = V
IL
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70C)
Min.
Max.
Unit
105
—
ns
—
105
ns
25
—
ns
—
25
ns
—
105
ns
—
25
ns
0
20
ns
0
20
ns
0
—
ns
Measurement conditions
Input signal level ··································· 0 V/3 V
Input timing reference level ·················· 1/2V
CC
Output load············································ 50 pF
Output timing reference level················ 1/2V
CC
Output load
Output
50 pF
(Including scope and jig)
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FEDR26V51252R-002-02
MR26V51252R / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
t
C
t
C
Address
t
CE
CE#
t
OE
OE#
t
ACC
Valid Data
Dout
Hi-Z
Valid Data
t
OH
t
ACC
t
OH
t
CHZ
t
OHZ
Hi-Z
Page Access Mode Read Cycle
t
C
A3 to A24
t
PC
A-1 to A2 (Byte mode)
A0 to A2 (Word mode)
t
CE
t
OH
t
PC
CE#
t
OE
OE#
t
CHZ
t
ACC
Dout
Hi-Z
t
PAC
t
PAC
t
OHZ
Hi-Z
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电源技术