FEDR26V6455J-002-02
Issue Date: Oct. 01, 2008
MR26V6455J
2M–Word
32–Bit or 4M–Word
16–Bit
Page Mode
P2ROM
PIN CONFIGURATION (TOP VIEW)
A0
1
A1
2
A2
3
A3
4
A4
5
A5
6
Vcc
7
70
NC
69
NC
68
A20
67
WORD#
66
OE#
65
CE#
64
Vss
63
D31/A-1
62
D15
61
D30/A-1
60
D14
59
Vss
58
Vcc
57
D29
56
D13
55
D28
54
D12
53
D27
52
D11
51
D26
50
D10
49
Vss
48
Vcc
47
D25
46
D9
45
D24
44
D8
43
Vcc
42
A19
41
A18
40
A17
39
A16
38
A15
37
A14
36
A13
FEATURES
· 2,097,152-word
32-bit / 4,194,304-word
16-bit
electrically switchable configuration
· Page size of 8-word x 32-Bit or 16-word x 16-Bit
· 3.0 V to 3.6 V power supply
·Random Access time
100 ns MAX
·Page Access time
30ns MAX
· Operating current
100 mA MAX
· Standby current
20 µA MAX
· Input/Output TTL compatible
· Three-state output
D0
8
D16
9
PACKAGES
· MR26V6455J-xxxMB
70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
D1
10
D17
11
Vss
12
Vcc
13
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM.
This exclusive LAPIS Semiconductor technology
utilizes factory test equipment for programming the
customers code into the P2ROM prior to final
production testing. Advancements in this technology
allows production costs to be equivalent to
MASKROM and has many advantages and added
benefits over the other non-volatile technologies,
which include the following;
· Short lead time,
since the P2ROM is programmed at
the final stage of the production process, a large
P2ROM inventory "bank system" of un-programmed
packaged products are maintained to provide an
aggressive lead-time and minimize liability as a
custom product.
· No mask charge,
since P2ROMs do not utilize a
custom mask for storing customer code, no mask
charges apply.
· No additional programming charge,
unlike Flash and
OTP that require additional programming and
handling costs, the P2ROM already has the code
loaded at the factory with minimal effect on the
production throughput. The cost is included in
the unit price.
· Custom Marking
is available at no additional charge.
D2
14
D18
15
D3
16
D19
17
D4
18
D20
19
D5
20
D21
21
Vss
22
Vcc
23
D6
24
D22
25
D7
26
D23
27
Vss
28
A6
29
A7
30
A8
31
A9
32
A10
33
A11
34
A12
35
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FEDR26V6455J-002-02
MR26V6455J / P2ROM
BLOCK DIAGRAM
A-1(D30/A-1[61] AND D31/A-1[63])
× 16/× 32 Switch
CE#
CE
OE#
OE
WORD#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
Row Decoder
Memory Cell Matrix
2M × 32-Bit or 4M × 16-Bit
Address Buffer
Column Decoder
Multiplexer
Output Buffer
D0 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30
D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31
In16-bit output mode, these pins
are placed in a high-Z state and
pin D31,D30 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D31 / A-1,D30/A-1
A0 to A20
D0 to D29
CE#
OE#
WORD#
V
CC
V
SS
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word -Byte select input
Power supply voltage
Ground
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FEDR26V6455J-002-02
MR26V6455J / P2ROM
FUNCTION TABLE
Mode
Read (32-Bit)
Read (16Bit)
Output disable
Standby
CE#
L
L
L
H
OE#
L
L
H
WORD#
H
L
H
L
H
L
V
CC
D0 to D15
D
OUT
3.3 V
D16 to D29
D
OUT
Hi–Z
Hi–Z
Hi–Z
D30/A–1,D31/A-1
L/H
:
Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Output short circuit current
Symbol
Ta
Tstg
V
I
V
O
V
CC
P
D
I
OS
Condition
—
Value
0 to 70
–55 to 125
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–0.5 to 5
1.0
10
Unit
°C
°C
V
V
V
W
mA
relative to V
SS
Ta = 25°C
—
RECOMMENDED OPERATING CONDITIONS
Parameter
V
CC
power supply voltage
Input “H” level
Input “L” level
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
= 3.0 to 3.6 V
Min.
3.0
2.2
–0.5
Typ.
—
—
—
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
V
CC
+0.5
V
0.6
V
Voltage is relative to V
SS
.
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input
WORD#
Output
Symbol
C
IN1
C
IN2
C
OUT
Condition
V
I
= 0 V
V
O
= 0 V
Min.
—
—
—
(V
CC
= 3.3 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
20
pF
—
400
—
20
3/8
FEDR26V6455J-002-02
MR26V6455J / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Typ.
Max.
Unit
—
10
A
—
10
A
—
20
A
—
1
mA
—
—
—
—
—
100
V
CC
+0.5
0.6
—
0.4
mA
V
V
V
V
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
I
LI
I
LO
I
CCSC
I
CCST
I
CCA1
V
IH
V
IL
V
OH
V
OL
Condition
V
I
= 0 to V
CC
V
O
= 0 to V
CC
CE# = V
CC
CE# = V
IH
CE# = V
IL
OE#= V
IH
tc = 5MHz
Min.
—
—
—
—
—
2.2
–0.5
2.4
—
—
—
I
OH
= –2 mA
I
OL
= 2 mA
Voltage is relative to V
SS
.
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Min.
Max.
Unit
100
—
ns
—
100
ns
30
—
ns
—
30
ns
—
100
ns
—
30
ns
0
20
ns
0
20
ns
0
—
ns
Parameter
Address cycle time
Address access time
Page cycle time
Page access time
CE# access time
OE# access time
Output disable time
Output hold time
Symbol
t
C
t
ACC
t
PC
t
PAC
t
CE
t
OE
t
CHZ
t
OHZ
t
OH
Condition
—
CE# = OE# = V
IL
—
CE# = OE# = V
IL
OE# = V
IL
CE# = V
IL
OE# = V
IL
CE# = V
IL
CE# = OE# = V
IL
Measurement conditions
Input signal level
0 V/3 V
Input timing reference level
1/2Vcc
Output load
50 pF
Output timing reference level 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
4/8
FEDR26V6455J-002-02
MR26V6455J / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
t
C
Address
t
OH
t
CE
CE#
t
CHZ
t
OE
OE#
t
ACC
Dout
Hi-Z
Valid Data
Valid Data
Hi-Z
t
OHZ
t
OH
t
ACC
t
C
Page Access Mode Read Cycle
t
C
A3 to A20
t
PC
A-1 to A2 (x16 mode)
A0 to A2 (x32 mode)
t
CE
t
OH
t
PC
CE#
t
OE
OE#
t
ACC
Dout
Hi-Z
Hi-Z
t
PAC
t
PAC
t
OHZ
t
CHZ
5/8
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