FEDR27T12800L-002-03
Issue Date: Jan.06, 2009
MR27T12800L
8M–Word
×
16–Bit or 16M–Word
×
8–Bit
P2ROM
PIN CONFIGURATION (TOP VIEW)
FEATURES
· 8,388,608-word
×
16-bit / 16,777,216-word
×
8-bit
electrically switchable configuration
· Access time
2.7 V to 3.6 V power supply 90 ns MAX
· Operating current
25 mA MAX(5MHz)
· Standby current
10 µA MAX
· Input/Output TTL compatible
· Three-state output
BYTE#
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
V
SS
47
V
SS
46
D15/A-1
45
D7
44
D14
43
D6
42
D13
41
D5
40
D12
39
D4
38
V
CC
37
V
CC
36
A22
35
D11
34
D3
33
D10
32
D2
31
D9
30
D1
29
D8
28
D0
27
OE#
26
V
SS
25
V
SS
PACKAGES
· MR27T12800L-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
48TSOP(Type-I)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time,
since the P2ROM is programmed at the final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive
lead-time and minimize liability as a custom product.
· No mask charge,
since P2ROMs do not utilize a custom mask for storing customer code, no mask charges
apply.
· No additional programming charge,
unlike Flash and OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput.
The cost is included in the unit price.
· Custom Marking is
available at no additional charge.
· Pin Compatible with Mask ROM.
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FEDR27T12800L-002-03
MR27T12800L / P2ROM
BLOCK DIAGRAM
A–1
× 8/× 16 Switch
CE#
CE
OE#
OE
BYTE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
Row Decoder
Memory Cell Matrix
8M × 16-Bit or 16M × 8-Bit
Address Buffer
Column Decoder
Multiplexer
Output Buffer
D0
D1
D2
D3
D4
D5
D6
D7
D8
D10
D9
D12
D14
D15
D11
D13
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A22
D0 to D14
CE#
OE#
BYTE#
V
CC
V
SS
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
Functions
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FEDR27T12800L-002-03
MR27T12800L / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
Output disable
Standby
∗:
Don’t Care (H or L)
CE#
L
L
L
H
OE#
L
L
H
∗
BYTE#
H
L
H
L
H
L
2.7 V
to
3.6 V
D
OUT
V
CC
D0 to D7
D8 to D14
D
OUT
Hi–Z
Hi–Z
Hi–Z
L/H
∗
∗
D15/A–1
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Output short circuit current
Symbol
Ta
Tstg
V
I
V
O
V
CC
P
D
I
OS
Ta = 25°C
—
relative to V
SS
Condition
—
Value
0 to 70
–55 to 125
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–0.5 to 5
1.0
10
Unit
°C
°C
V
V
V
W
mA
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
CC
+0.5∗
0.6
V
V
V
Parameter
V
CC
power supply voltage
Input “H” level
Input “L” level
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
= 2.7 to 3.6 V
Min.
2.7
2.2
–0.5∗∗
Typ.
—
—
—
Voltage is relative to V
SS
.
∗
: Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗
: -1.5V (Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(V
CC
= 3.0 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
—
—
10
200
10
pF
Parameter
Input
BYTE#
Output
Symbol
C
IN1
C
IN2
C
OUT
Condition
V
I
= 0 V
V
O
= 0 V
Min.
—
—
—
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FEDR27T12800L-002-03
MR27T12800L / P2ROM
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(V
CC
= 2.7 V to 3.6 V, Ta = 0 to 70°C)
Min.
Typ.
Max.
Unit
—
—
—
—
—
2.2
–0.5∗∗
2.4
—
—
—
—
—
—
—
—
—
—
10
10
10
1
25
V
CC
+0.5∗
0.6
—
0.4
μA
μA
μA
mA
mA
V
V
V
V
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
I
LI
I
LO
I
CCSC
I
CCST
I
CCA
V
IH
V
IL
V
OH
V
OL
Condition
V
I
= 0 to V
CC
V
O
= 0 to V
CC
CE# = V
CC
CE# = V
IH
CE# = V
IL
, OE# = V
IH
f=5MHz
—
—
I
OH
= –1 mA
I
OL
= 2 mA
Voltage is relative to V
SS
.
∗
: Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗
: -1.5V (Min.) when pulse width of undershoot is less than 10ns.
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FEDR27T12800L-002-03
MR27T12800L / P2ROM
AC CHARACTERISTICS
(V
CC
= 2.7 V to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
90
—
—
—
0
0
0
—
90
90
30
20
20
—
ns
ns
ns
ns
ns
ns
ns
Parameter
Address cycle time
Address access time
CE# access time
OE# access time
Output disable time
Output hold time
Symbol
t
C
t
ACC
t
CE
t
OE
t
CHZ
t
OHZ
t
OH
Condition
—
CE# = OE# = V
IL
OE# = V
IL
CE# = V
IL
OE# = V
IL
CE# = V
IL
CE# = OE# = V
IL
Measurement conditions
Input signal level ................................... 0 V / Vcc
Input timing reference level................... 1/2Vcc
Output load ........................................... 50 pF
Output timing reference level ................ 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
5/9
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