FEDR27V3241L-002-04
Issue Date: Oct .01, 2008
MR27V3241L
32M–Word
×
1–Bit Serial Production Programmed ROM (P2ROM)
GENERAL DESCRIPTION
The MR27V3241L is a 32 Mbit Production Programmed Read-Only Memory, which is configured as 33,554,432
word
×
1-bit. The MR27V3241L supports a simple read operation using a single 3.3V power supply and a Serial
Peripheral Interface (SPI) compatible serial bus.
The MR27V3241L have data programmed and have functions tested at LAPIS Semiconductor factory. (Using the
DC pins for the programming function is NOT allowed.)
FEATURES
· 33,554,432-word
×
1-bit configuration
· +3.0 V to 3.6 V power supply
· Access time
33 MHz serial clock (FAST-READ)
20 MHz serial clock (READ)
· Read Identification Instruction
· Active read current
40 mA MAX (FAST-READ)
20 mA MAX (READ)
· Standby current
50 µA MAX
· Serial Clock Input and Data Input/Output
· Input Data Format
1-byte command code, 3-byte address, 1-byte dummy
(FAST-READ)
1-byte command code, 3-byte address
(READ)
PIN CONFIGURATION (TOP VIEW)
NC
V
CC
NC
DC
NC
NC
#CS
SO
1
2
3
4
5
6
7
8
16
SCLK
15
SI
14
NC
13
NC
12
NC
11
NC
10
V
SS
9
NC
16SOP
PACKAGES
· MR27V3241L-xxxMP
16-pin plastic SOP (P-SOP16-375-1.27-K)
PIN DESCRIPTIONS
Pin name
#CS
SI
SO
SCLK
V
CC
V
SS
DC
NC
Chip Select
Serial Data Input
Serial Data Output
Clock Input
Power supply voltage
Ground
Don’t care ( 0v - Vcc )
<for reference> Program power supply voltage Vpp under Programming operation
No connection
Functions
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FEDR27V3241L-002-04
MR27V3241L / P2ROM
READ COMMAND DEFINITION
Command
1st
2nd
3rd
4th
Action
03[H]
AD1
AD2
AD3
N byte read out until #CS goes high
Read Array (byte)
Note
1
2
2
2
3
Note:
st
1. The 1 command 03[H] is a Read command
2. AD1 to AD3 are address input data
3. Data output
Details of Command are shown as follows.
1-byte command code
READ:
0
3-byte address
AD1:
AD2:
AD3:
X
A15
A7
0
X
A14
A6
0
A21
A13
A5
0
A20
A12
A4
0
A19
A11
A3
0
A18
A10
A2
1
A17
A9
A1
1
A16
A8
A0
Note:
X: Dummy bit
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FEDR27V3241L-002-04
MR27V3241L / P2ROM
FAST-READ COMMAND DEFINITION
Command
1st
2nd
3rd
4th
5th
Action
0B[H]
AD1
AD2
AD3
X
N byte read out until #CS goes high
Read Array (byte)
Note
1
2
2
2
3
4
Note:
st
1. The 1 command 0B[H] is a Read command
2. AD1 to AD3 are address input data
3. X is a dummy cycle
4. Data output
Details of Command are shown as follows.
1-byte command code
FAST-READ:
3-byte address
AD1:
AD2:
AD3:
0
X
A15
A7
0
X
A14
A6
0
A21
A13
A5
0
A20
A12
A4
1
A19
A11
A3
0
A18
A10
A2
1
A17
A9
A1
1
A16
A8
A0
Note:
X: Dummy bit
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FEDR27V3241L-002-04
MR27V3241L / P2ROM
READ IDENTIFICATION COMMAND DEFINITION
Command
1
st
Read Array (byte)
9F[H]
3 byte read out
Note
1
2
Action
Note:
st
1. The 1 command 9F[H] is a Read Identification command
2. Identification output
Details of Command are shown as follows.
1-byte command code
RDID
1
0
0
1
1
1
1
1
IDENTIFICATION DEFINITION
Manufacturer Identification
AE[H]
Device Identification
Type
41[H]
Capacity
14[H]
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FEDR27V3241L-002-04
MR27V3241L / P2ROM
DEVICE OPERATION
1. Command “03h” or “0Bh” makes this LSI become and keep active mode until next #CS High.
2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO
pin is High-Z.
COMMAND DESCRIPTION
1. Read Array
This command consists of the 4-byte code. The 1
st
code is a command which decides if the device becomes
standby or active mode. The 1
st
code “03h”activates the device. The 2
nd
code to the 4
th
code are address.
2. Fast-Read Array
This command consists of the 5-byte code. The 1
st
code is a command which decides if the device becomes
standby or active mode. The 1
st
code “0Bh”activates the device. The 2
nd
code to the 4
th
code are address. The 5
th
code is a dummy cycle.
3. Read Identification Array
This command consists of the 1-byte code. The 1
st
code is a command which decides if the device becomes
standby or active mode. The 1
st
code “9Fh”activates the device.
4. Standby
When #CS is high , the device is put in standby mode at the next rising edge of SCLK. Maximum standby
current is 50uA. When the above-mentioned 1
st
code is incorrect command , the device is put in standby mode
at the next rising edge of SCLK.
DATA SEQUENCE
The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is
also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input
and output data are bit7 (MSB) first, bit6, bit5, …, and bit0(LSB).
ADDRESS SEQUENCE
The address assignment is described at the COMMAND DEFINITION on page 2 or 3.
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