MR2A16A
FEATURES
• Fast 35 ns Read/Write cycle
• SRAM compatible timing, uses existing SRAM control-
lers without redesign
• Unlimited Read & Write endurance
• Data non-volatile for >20 years at temperature
• One memory replaces Flash, SRAM, EEPROM and
BBSRAM in a system for simpler, more efficient design
• Replaces battery-backed SRAM solutions with MRAM
to improve reliability
• 3.3 volt power supply
• Automatic data protection on power loss
• Commercial, Industrial, Extended temperatures
• AEC-Q100 Grade 1 option
• All products meet MSL-3 moisture sensitivity level
• RoHS-compliant SRAM TSOP2 and BGA Packages
256K x 16 MRAM Memory
44-pin TSOP2
48-ball BGA
INTRODUCTION
RoHS
The MR2A16A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device orga-
nized as 262,144 words of 16 bits. The MR2A16A offers SRAM compatible 35 ns read/write timing
with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automati-
cally protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of
specification.
The MR2A16A is the ideal memory solution for applications that must permanently store and re-
trieve critical data and programs quickly.
The M2A16A is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin
small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM
products and other nonvolatile RAM products.
The MR2A16A provides highly reliable data storage over a wide range of temperatures. The prod-
uct is offered with Commercial (0 to +70 °C), Industrial (-40 to +85 °C), Extended (-40 to +105 °C),
and AEC-Q100 Grade 1 (-40 to +125 °C) operating temperature range options.
Copyright © Everspin Technologies 2015
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MR2A16A Rev. 11.2, 6/2015
MR2A16A
TABLE OF CONTENTS
FEATURES .............................................................................................................................................1
INTRODUCTION ...................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4
Figure 1 – Block Diagram ........................................................................................................................................... 4
Table 1 – Pin Functions ............................................................................................................................................... 4
Figure 2 – Pin Diagrams for Available Packages (Top View) .......................................................................... 5
Table 2 – Operating Modes ....................................................................................................................................... 5
ABSOLUTE MAXIMUM RATINGS .........................................................................................................6
Table 3 – Absolute Maximum Ratings ................................................................................................................... 6
OPERATING CONDITIONS ...................................................................................................................7
Power Up and Power Down Sequencing .......................................................................................8
Figure 3 – Power Up and Power Down Diagram ............................................................................................... 8
DC CHARACTERISTICS .........................................................................................................................9
Table 4 – DC Characteristics ...................................................................................................................................... 9
Table 5 – Power Supply Characteristics ................................................................................................................ 9
TIMING SPECIFICATIONS ................................................................................................................. 10
Table 6 – Capacitance ...............................................................................................................................................10
Table 7 – AC Measurement Conditions ..............................................................................................................10
Figure 4 – Output Load Test Low and High .......................................................................................................10
Figure 5 – Output Load Test All Others ...............................................................................................................10
Read Mode .................................................................................................................................... 11
Table 8 – Read Cycle Timing ...................................................................................................................................11
Figure 6 – Read Cycle 1 .............................................................................................................................................11
Figure 7 – Read Cycle 2 .............................................................................................................................................11
Write Mode.................................................................................................................................... 12
Table 9 – Write Cycle Timing 1 (W Controlled) .................................................................................................12
Copyright © Everspin Technologies 2015
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MR2A16A Rev. 11.2, 6/2015
MR2A16A
TABLE OF CONTENTS (CONT’D)
Figure 8 – Write Cycle Timing 1 (W Controlled) ...............................................................................................12
Table 10 – Write Cycle Timing 2 (E Controlled) ................................................................................................13
Figure 9 – Write Cycle Timing 2 (E Controlled) .................................................................................................13
Table 11 – Write Cycle Timing 3 (LB / UB Controlled) ....................................................................................14
Figure 10 – Write Cycle Timing 3 (LB / UB Controlled) ..................................................................................14
ORDERING INFORMATION ............................................................................................................... 15
Table 12 – Ordering Part Number System for Parallel I/O MRAM..............................................................15
Table 13 – MR2A16A Ordering Part Numbers ..................................................................................................16
PACKAGE OUTLINE DRAWINGS ....................................................................................................... 17
Figure 11 – 44-TSOP2 Package Outline...............................................................................................................17
Figure 12 – 48-FBGA Packge Outline ...................................................................................................................18
REVISION HISTORY ........................................................................................................................... 19
HOW TO CONTACT US ....................................................................................................................... 20
Copyright © Everspin Technologies 2015
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MR2A16A Rev. 11.2, 6/2015
MR2A16A
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – Block Diagram
Table 1 – Pin Functions
Signal Name
A
E
W
G
UB
LB
Function
Address Input
Chip Enable
Write Enable
Output Enable
Upper Byte Enable
Lower Byte Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection
DQ
V
DD
V
SS
DC
NC
Copyright © Everspin Technologies 2015
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MR2A16A Rev. 11.2, 6/2015
MR2A16A
Figure 2 – Pin Diagrams for Available Packages (Top View)
A
A
A
A
A
E
DQL0
DQL1
DQL2
DQL3
V
DD
V
SS
DQL4
DQL5
DQL6
DQL7
W
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
G
UB
LB
DQU15
DQU14
DQU13
DQU12
V
SS
V
DD
DQU11
DQU10
DQU9
DQU8
DC
A
A
A
A
A
1
LB
DQU8
2
G
UB
DQU10
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
E
DQL1
6
NC
DQL0
A
B
C
D
E
F
G
H
DQU9
DQL2
V
SS
V
DD
DQU14
DQU11
DQL3
V
DD
V
SS
DQL6
DQU12
DQL4
DQU13
DQL5
DQU15
NC
A8
W
A11
DQL7
NC
DC
44-Pin TSOP Type2
48-Pin BGA
Table 2 – Operating Modes
E
1
H
L
L
L
L
L
L
L
L
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
G
1
X
H
X
L
L
L
X
X
X
W
1
LB
1
UB
1
X
H
X
H
H
H
L
L
L
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
Mode
Not selected
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDR
I
DDR
I
DDR
I
DDW
I
DDW
I
DDW
DQL[7:0]
2
Hi-Z
Hi-Z
Hi-Z
D
Out
Hi-Z
D
Out
D
in
Hi-Z
D
in
DQU[15:8]
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
Out
D
Out
Hi-Z
D
in
D
in
Copyright © Everspin Technologies 2015
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MR2A16A Rev. 11.2, 6/2015
FPGA/CPLD
