FEDR36V02G54B-002-01
Issue Date: Oct. 01, 2008
MR36V02G54B
64M–Word
×
32–Bit
Page Mode
P2ROM
PIN CONFIGURATION (TOP VIEW)
Vcc
Vss
A24
A23
A22
A21
A20
A19
A18
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
D28
69
D20
68
D12
67
D4
66
D29
65
D21
64
D13
63
D5
62
D30
61
D22
60
D14
59
D6
58
D31
57
D23
56
D15
55
D7
54
OE#
53
A_1
52
A0
51
Vcc
50
WORD#
49
Vss
48
D0
47
D8
46
D16
45
D24
44
D1
43
D9
42
D17
41
D25
40
Vcc
39
D2
38
D10
37
D18
36
D26
FEATURES
· 64Mx32 or 128Mx16-bit
electrically switchable configuration
· Page size of 8-word x 32-Bit or 16-word x 16-Bit
· 3.0 V to 3.6 V power supply
· Random Access time
105 ns MAX
· Page Access time
25 ns MAX
· Operating current 100 mA MAX
· Standby current
50 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
·70-pin plastic SSOP (P-SSOP70-500-0.80-EK-MC)
A16
A15
A14
A25
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits
over the other non-volatile technologies, which include the
following;
· Short lead time,
since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge,
since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge,
unlike Flash and OTP
that require additional programming and handling costs, the
P2ROM already has the code loaded at the factory with
minimal effect on the production throughput. The cost is
included in the unit price.
· Custom Marking
is available at no additional charge.
CE#
A13
A12
A11
Vcc
Vss
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Vss
D27
D19
D11
D3
70-pin SSOP
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
BLOCK DIAGRAM
A-1
× 16/× 32 Switch
CE#
CE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
OE#
OE
WORD#
Row Decoder
Memory Cell Matrix
64M × 32-Bit or 128M × 16-Bit
Address Buffer
Column Decoder
Multiplexer & Sense Amp.
Output Buffer
D0 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30
D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 D27 D29 D31
In16-bit output mode, these pins
are placed in a high-Z state
PIN DESCRIPTIONS
Pin name
A0 to A25
A–1
D0 to D31
CE#
OE#
WORD#
V
CC
V
SS
Functions
Address inputs
Address -1 input
Data outputs
Chip enable input
Output enable input
Word -Byte select input
Power supply voltage
Ground
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FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
FUNCTION TABLE
Mode
Read (32-Bit)
Read (16Bit)
Output
disable
Standby
CE#
L
L
L
H
OE#
L
L
H
∗
WORD#
H
L
H
L
H
L
V
CC
D0 to D15
D16 to D31
D
OUT
D
OUT
3.3 V
Hi–Z
Hi–Z
Hi–Z
A-1
∗
L/H
∗
∗
∗:
Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Output short circuit current
Power dissipation per package
Symbol
Ta
Tstg
V
I
V
O
V
CC
Ios
P
D
Condition
—
Value
0 to 70
–55 to 125
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–0.5 to 4.6
10
1.0
Unit
°C
°C
V
V
V
mA
W
relative to V
SS
—
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
Parameter
V
CC
power supply voltage
Input “H” level
Input “L” level
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
= 3.0 to 3.6 V
Min.
3.0
2.2
–0.5∗∗
Typ.
—
—
—
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
V
CC
+0.5∗
V
0.6
V
Voltage is relative to V
SS
.
∗
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input(except Word#)
Output
Symbol
C
IN1
C
OUT
Condition
V
I
= 0 V
V
O
= 0 V
Min.
—
—
(V
CC
= 3.3 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
20
pF
—
20
pF
3/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
I
LI
I
LO
I
CCSC
I
CCA1
V
IH
V
IL
V
OH
V
OL
Condition
V
I
= 0 to V
CC
V
O
= 0 to V
CC
CE# =
Add.=V
CC
CE# = V
IL
OE# = V
IH
—
—
I
OH
= –2 mA
I
OL
= 2 mA
V
CC
=3.6V
tc = 200 ns
Min.
—
—
—
—
2.2
–0.5∗∗
2.4
—
Typ.
—
—
—
—
—
—
—
—
Max.
20
20
50
100
V
CC
+0.5
∗
0.6
—
0.4
Unit
μA
μA
mA
mA
V
V
V
V
Voltage is relative to V
SS
.
∗
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗
: -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(V
CC
= 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Address cycle time
Address access time
Address skew time
CE Address skew time
Page cycle time
Page access time
CE# access time
OE# access time
Output disable time
Output hold time
Symbol
t
C
t
ACC
t
ASK
T
CSK
t
PC
t
PAC
t
CE
t
OE
t
CHZ
t
OHZ
t
OH
Condition
Address access
CE# access
—
—
—
—
CE# = OE# = V
IL
OE# = V
IL
CE# = V
IL
OE# = V
IL
CE# = V
IL
CE# = OE# = V
IL
Min.
105
105
—
—
—
25
—
—
—
0
0
0
Max.
—
—
105
10
10
—
25
105
25
20
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measurement conditions
Input signal level------------------------------------
Input timing reference level ----------------------
Output load ------------------------------------------
Output timing reference level--------------------
Output load
Output
0 V/3 V
1/2Vcc
50 pF
1/2Vcc
50 pF
(Including scope and jig)
4/9
FEDR36V02G54B-002-01
MR36V02G54B / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
t
C
Address
t
CE
CE#
t
OE
OE#
t
ACC
Dout
Valid Data
Hi-Z
Valid Data
Hi-Z
t
OHZ
t
OH
t
ASK
t
OH
t
ACC
t
C
t
CHZ
Page Access Mode Read Cycle
t
C
A3 to A25
t
PC
A-1 to A2 (X16 mode)
A0 to A2 (X32 mode)
t
CE
t
OH
t
PC
CE#
t
CSK
t
OE
OE#
t
CHZ
t
ACC
Dout
Hi-Z
t
PAC
t
PAC
t
OHZ
Hi-Z
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模拟电子