MR4A16B
FEATURES
•
+3.3 Volt power supply
•
Fast 35 ns read/write cycle
•
SRAM compatible timing
•
Unlimited read & write endurance
•
Data always non-volatile for >20 years at temperature
•
RoHS-compliant small footprint BGA and TSOP2 package
•
AEC-Q100 Grade 1 option in TSOP2 package.
1M x 16 MRAM
BENEFITS
•
One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems
for simpler, more efficient designs
•
Improves reliability by replacing battery-backed SRAM
INTRODUCTION
The MR4A16B is a 16,777,216-bit magnetoresistive random access memory
(MRAM) device organized as 1,048,576 words of 16 bits. The MR4A16B offers
SRAM compatible 35 ns read/write timing with unlimited endurance. Data
is always non-volatile for greater than 20 years. Data is automatically pro-
tected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To
simplify fault tolerant design, the MR4A16B includes internal single bit error correction code with 7 ECC
parity bits for every 64 data bits. The MR4A16B is the ideal memory solution for applications that must
permanently store and retrieve critical data and programs quickly.
RoHS
The
MR4A16B
is available in a small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small
outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and
other nonvolatile RAM products.
The
MR4A16B
provides highly reliable data storage over a wide range of temperatures. The product is
offered with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), and AEC-Q100
Grade 1 (-40 to +125 °C) temperature range options.
CONTENTS
1. DEVICE PIN ASSIGNMENT.........................................................................
2. ELECTRICAL SPECIFICATIONS.................................................................
3. TIMING SPECIFICATIONS..........................................................................
4. ORDERING INFORMATION.......................................................................
5. MECHANICAL DRAWING..........................................................................
6. REVISION HISTORY......................................................................................
How to Reach Us...................................................................................... ..........
1
3
4
7
12
13
15
15
MR4A16B Rev. 9.1 1/2014
Copyright © Everspin Technologies 2014
MR4A16B
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
G
OUTPUT
ENABLE
BUFFER
10
10
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
8
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
UPPER
BYTE
OUTPUT
BUFFER
A[19:0]
20
ADDRESS
BUFFER
8
E
CHIP
ENABLE
BUFFER
16
1M x 16
BIT
MEMORY
ARRAY
16
8
LOWER
BYTE
OUTPUT
BUFFER
UPPER
BYTE
WRITE
DRIVER
8
W
WRITE
ENABLE
BUFFER
8
FINAL
WRITE
DRIVERS
8
8
DQU[15:8]
UB
LB
UB
BYTE
ENABLE
BUFFER
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
LOWER
BYTE
WRITE
DRIVER
8
DQL[7:0]
LB
Table 1.1 Pin Functions
Signal Name
A
E
W
G
UB
LB
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Upper Byte Enable
Lower Byte Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection
Copyright © Everspin Technologies 2014
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MR4A16B Rev. 9.1 1/2014
DEVICE PIN ASSIGNMENT
Figure 1.1 Pin Diagrams for Available Packages (Top View)
1
LB
DQU8
MR4A16B
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
E
DQL1
2
G
UB
DQU10
3
A0
A3
A5
A17
DC
A14
A12
A9
6
NC
DQL0
A
B
C
D
E
F
G
H
NC
A
A
A
A
A
A
E
DQ
DQ
DQ
DQ
V
DD
V
SS
DQ
DQ
DQ
DQ
W
A
A
A
A
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
A
A
A
A
G
UB
LB
DQ
DQ
DQ
DQ
V
SS
V
DD
DQ
DQ
DQ
DQ
DC
A
A
A
A
A
NC
NC
NC
DQU9
DQL2
V
SS
V
DD
DQU14
DQU11
DQL3
V
DD
V
SS
DQL6
DQU12
DQL4
DQU13
DQL5
DQU15
NC
A8
W
A11
DQL7
A18
A19
48-Pin BGA
Table 1.2 Operating Modes
54-Pin TSOP2
E
1
H
L
L
L
L
L
L
L
L
1
2
G
1
X
H
X
L
L
L
X
X
X
W
1
X
H
X
H
H
H
L
L
L
LB
1
X
X
H
L
H
L
L
H
L
UB
1
X
X
H
H
L
L
H
L
L
Mode
Not selected
Output disabled
Output disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDR
I
DDR
I
DDR
I
DDW
I
DDW
I
DDW
DQL[7:0]
2
Hi-Z
Hi-Z
Hi-Z
D
Out
Hi-Z
D
Out
D
in
Hi-Z
D
in
DQU[15:8]
2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
Out
D
Out
Hi-Z
D
in
D
in
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © Everspin Technologies 2014
3
MR4A16B Rev. 9.1 1/2014
MR4A16B
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any
voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken
to avoid application of any magnetic field greater than the maximum field intensity specified
in the maximum ratings.
Table 2.1 Absolute Maximum Ratings
1
Symbol
V
DD
V
IN
I
OUT
P
D
T
BIAS
T
stg
T
Lead
H
max_write
H
max_read
1
Parameter
Supply voltage
2
Voltage on an pin
2
Output current per pin
Package power dissipation
3
Conditions
Value
-0.5 to 4.0
-0.5 to V
DD
+ 0.5
±20
0.600
Unit
V
V
mA
W
°C
°C
°C
°C
°C
A/m
Commercial
Temperature under bias
Storage Temperature
Lead temperature during solder (3
minute max)
Maximum magnetic field
Maximum magnetic field
During Write
During Read or Standby
Industrial
AEC-Q100 Grade 1
-10 to 85
-45 to 95
-45 to 130
-55 to 150
260
8000
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic
fields could affect device reliability.
All voltages are referenced to V
SS
. The DC value of V
IN
must not exceed actual applied V
DD
by more than
0.5V. The AC value of V
IN
must not exceed applied V
DD
by more than 2V for 10ns with I
IN
limited to less than
20mA.
Power dissipation capability depends on package characteristics and use environment.
2
3
Copyright © Everspin Technologies 2014
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MR4A16B Rev. 9.1 1/2014
Electrical Specifications
Table 2.2 Operating Conditions
Symbol
V
DD
V
WI
V
IH
V
IL
T
A
Parameter
Power supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
Commercial
Temperature under bias
Industrial
AEC-Q100 Grade 1
4
1
2
3
4
MR4A16B
Temp Range
Min
3.0
1
2.5
2.2
-0.5
3
0
-40
-40
Typical
3.3
2.7
-
-
-
-
-
Max
3.6
3.0
1
V
DD
+ 0.3
2
0.8
70
85
125
Unit
V
V
V
V
°C
°C
°C
There is a 2 ms startup time once V
DD
exceeds V
DD,
(min). See
Power Up and Power Down Sequencing
below.
V
IH
(max) = V
DD
+ 0.3 V
DC
; V
IH
(max) = V
DD
+ 2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
V
IL
(min) = -0.5 V
DC
; V
IL
(min) = -2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life).
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever V
DD
is less than V
WI
. As soon as V
DD
exceeds V
DD
(min),
there is a startup time of 2 ms before read or write operations can start. This time allows memory power
supplies to stabilize.
The E and W control signals should track V
DD
on power up to V
DD
- 0.2 V or V
IH
(whichever is lower) and remain
high for the startup time. In most systems, this means that these signals should be pulled up with a resis-
tor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W
should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where V
DD
goes below V
WI
, writes are protected and a startup time must be
observed when power returns above V
DD
(min).
Figure 2.1 Power Up and Power Down Diagram
V
WI
V
DD
BROWNOUT or POWER LOSS
2 ms
STARTUP
2 ms
RECOVER
NORMAL
OPERATION
READ/WRITE
INHIBITED
NORMAL
OPERATION
READ/WRITE
INHIBITED
V
IH
V
IH
E
W
Copyright © Everspin Technologies 2014
5
MR4A16B Rev. 9.1 1/2014
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