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MS18R1622(4/8)EH0

Revision History

Version 0.1 (February 2004) -

Preliminary

- First Copy

- Based on the 1.0 ver. (July 2002) 288Mbit D-die SO-RIMM

™

Module Datasheet.

Version 1.0 (May 2004)

- Eliminate "Preliminary"

Page 0

Rev. 1.0 May 2004

MS18R1622(4/8)EH0

(

16Mx18)*2(4/8)pcs SO-RIMM™ based on 288Mb E-die, 32s banks,16K/32ms Refresh, 2.5V

Overview

The SO-RIMM™ module is a general purpose high-perfor-

mance memory subsystem suitable for a broad range of

applications including networking systemsnetworking

systems, digital con sumer systems, mobile

"Thin

and light"

PCs, and other applications where high bandwidth and low

latency are required.

The SO-RIMM module consists of 288Mb RDRAM

devices.These are extremely high speed CMOS DRAMs

organized as 16M words by 18 bits. The use of Rambus

Signaling Level(RSL) technology permits up to 1066MHz

transfer rates while using conventional system and board

design technologies. RDRAM devices are capable of

sustained data transfers up to at 0.94ns per two bytes (7.5ns

per 16 bytes)

The RDRAM Architecture enables the highest sustained

bandwidth for multiple, simultaneous, randomly addressed,

memory transactions. The seperate control and data buses

with independent row and column control yield high bus

efficiency. The RDRAM device’s thirty-two bank architec-

ture supports up to four simultaneous transactions per

device.



Key Timing Parameters/Part Numbers

The following table lists the frequency and latency bins

available for SO-RIMM modules.

Table 1: Part Number by Freq. & Latency

Speed

Organization

Bin

rac

(Row

Access

(MHz)

Time) ns

1066

800

1066

800

1066

800

32P

I/O

Freq.

Part Number

-CT9

32M x 18

-CM8

-CK8

-CT9

64M x 18

-CM8

-CK8

-CT9

128M x 18

-CM8

-CK8

MS18R1622EH0-CT9

MS18R1622EH0-CM8

MS18R1622EH0-CK8

MS18R1624EH0-CT9

MS18R1624EH0-CM8

MS18R1624EH0-CK8

MS18R1628EH0-CT9

MS18R1628EH0-CM8

MS18R1628EH0-CK8

Features

♦

High speed of 1066MHz and 800MHz per pin

♦

160 edge connector pads with 0.65mm pad spacing

♦

Maximum module PCB size : 67.6mm x 31.25mm x

Form Factor

The SO-RIMM modules are offered in 160-pad 0.65mm

edge connector pad pitch form factor suitable for 160 contact

SO-RIMM connectors. Figure 1 below, shows a eight device

SO-RIMM module.

1.00mm (2.66” x 1.23” x 0.039”)

♦

Each RDRAM device has 32 banks, for a total of

256,128,64 banks on each 288MB,144MB,72MB module

respectively

♦

Gold plated edge connector pad contacts

♦

Serial Presence Detect(SPD) support

♦

Operates from a 2.5 volt supply (± 5%)

♦

Low power and powerdown self refresh modes

♦

Sperate Row and Column buses for heigher efficiency

♦

WBGA lead free package SO-RIMM Module(92 balls)

Note: On double sided modules, RDRAM devices are also installed on bottom side of PCB.

Figure 1: SO-RIMM Module shown with heat spreader removed

Page 1

Rev. 1.0 May 2004

MS18R1622(4/8)EH0

Table 2: Module Pad Numbers and Signal Names

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

Pin Name

Gnd

LDQA8

Gnd

LDQA6

Gnd

LDQA4

Gnd

LDQA2

Gnd

LDQA0

Gnd

LCTM

Gnd

LCTMN

Gnd

LROW1

Gnd

LCOL4

Gnd

LCOL2

Gnd

LCOL0

Gnd

LDQB0

Gnd

LDQB2

Gnd

LDQB4

Gnd

LDQB6

Gnd

LSCK

Gnd

SOUT

Vdd

Gnd

Vcmos

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

Pin Name

Gnd

LDQA7

Gnd

LDQA5

Gnd

LDQA3

Gnd

LDQA1

Gnd

LCFM

Gnd

LCFMN

Gnd

LROW2

Gnd

LROW0

Gnd

LCOL3

Gnd

LCOL1

Gnd

LDQB1

Gnd

LDQB3

Gnd

LDQB5

Gnd

LDQB7

Gnd

LDQB8

Gnd

LCMD

Gnd

SIN

Vdd

Gnd

Vcmos

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

Pin Name

Vref

SCL

Vdd

SDA

Vdd

SVdd

Gnd

RSCK

Gnd

RDQB8

Gnd

RDQB7

Gnd

RDQB5

Gnd

RDQB3

Gnd

RDQB1

Gnd

RCOL1

Gnd

RCOL3

Gnd

RROW0

Gnd

RROW2

Gnd

RCFMN

Gnd

RCFM

Gnd

RDQA1

Gnd

RDQA3

Gnd

RDQA5

Gnd

RDQA7

Gnd

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

B74

B75

B76

B77

B78

B79

B80

Pin Name

Vref

SA0

Vdd

SA1

Vdd

SWP

Gnd

RCMD

Gnd

RDQB6

Gnd

RDQB4

Gnd

RDQB2

Gnd

RDQB0

Gnd

RCOL0

Gnd

RCOL2

Gnd

RCOL4

Gnd

RROW1

Gnd

RCTMN

Gnd

RCTM

Gnd

RDQA0

Gnd

RDQA2

Gnd

RDQA4

Gnd

RDQA6

Gnd

RDQA8

Gnd

Page 2

Rev. 1.0 May 2004

MS18R1622(4/8)EH0

Table 3 : Module Connector Pad Description

Signal

Pins

A1, A3, A5, A7, A9, A11, A13, A15,

A17, A19, A21, A23, A25, A27, A29,

A31, A33, A37, A48, A50, A52, A54,

A56, A58, A60, A62, A64, A66, A68,

A70, A72, A74, A76, A78, A80,

B1, B3, B5, B7, B9, B11, B13, B15,

B17, B19, B21, B23, B25, B27, B29,

B31, B33, B37, B48, B50, B52, B54,

B56, B58, B60, B62, B64, B66, B68,

B70, B72, B74, B76, B78, B80

B10

B12

B32

A18, B18, A20, B20, A22

A12

A14

RSL

CMOS

RSL

I/O

Type

Description

Gnd

Ground reference for RDRAM core and interface. 72 pins.

LCFM

LCFMN

LCMD

LCOL4..

LCOL0

LCTM

LCTMN

LDQA8..

LDQA0

LDQB8..

LDQB0

LROW2..

LROW0

LSCK

RCFM

RCFMN

RCMD

RCOL4..

RCOL0

Clock from master. Interface clock used for receiving RSL

signals from the Channel. Positive polarity.

Clock from master. Interface clock used for receiving RSL

signals from the Channel. Negative polarity.

Serial Command Pin. Pin used to read from and write to the

control registers. Also used for power management.

Column bus. 5-bit bus containing control and address infor-

mation for column accesses.

Clock to master. Interface clock used for transmitting RSL

signals to the Channel. Positive polarity.

Clock to master. Interface clock used for transmitting RSL

signals to the Channel. Negative polarity.

Data bus A. A 9-bit bus carrying a byte of read or write data

between the Channel and the RDRAM device. LDQA8 is

non-functional on modules with x16 RDRAM devices

Data bus B. A 9-bit bus carrying a byte of read or write data

between the Channel and the RDRAM device. LDQB8 is non-

functional on modules with x16 RDRAM devices.

Row bus. 3-bit bus containing control and address information

for row accesses.

Serial Clock input. Clock source used to read from and write

to the RDRAM control registers.

These pads are not connected. These 24 connector pads are

reserved for future use.

A2, B2, A4, B4, A6, B6, A8, B8, A10

I/O

RSL

B30, B28, A30, B26, A28, B24, A26,

B22, A24

B14, A16, B16

A32

A36, B36, A38, B38, A40, B40, A41,

B41

A71

A69

B49

B63, A63, B61, A61, B59

I/O

RSL

CMOS

RSL

CMOS

RSL

Clock from master. Interface clock used for receiving RSL

signals from the Channel. Positive polarity.

Clock from master. Interface clock used for receiving RSL

signals from the Channel. Negative polarity.

Serial Command Input. Pin used to read from and write to the

control registers. Also used for power management.

Column bus. 5-bit bus containing control and address infor-

mation for column accesses.

Page 3

Rev. 1.0 May 2004

MS18R1622(4/8)EH0

Signal

RCTM

RCTMN

RDQA8..

RDQA0

RDQB8..

RDQB0

RROW2..

RROW0

RSCK

SA0

SA1

SCL

SDA

B69

B67

B79, A79, B77, A77, B75, A75, B73,

A73, B71

A51, A53, B51, A55, B53, A57, B55,

A59, B57

A67, B65, A65

A49

B43

B45

A43

A45

Pins

I/O

Type

RSL

Description

Clock to master. Interface clock used for transmitting RSL

signals to the Channel. Positive polarity.

Clock to master. Interface clock used for transmitting RSL

signals to the Channel. Negative polarity.

Data bus A. A 9-bit bus carrying a byte of read or write data

between the Channel and the RDRAM device. RDQA8 is

non-functional on modules x16 RDRAM devices.

Data bus B. A 9-bit bus carrying a byte of read or write data

between the Channel and the RDRAM device. RDQB8 is

non-functional on modules x16 RDRAM devices.

Row bus. 3-bit bus containing control and address information

for row accesses.

Serial Clock input. Clock source used to read from and write

to the RDRAM control registers.

Serial Presence Detect Address 0.

Serial Presence Detect Address 1.

Serial Presence Detect Clock.

Serial Presence Detect Data (Open Collector I/O).

Serial I/O. Pin for reading from and writing to the control reg-

isters. Attaches to SIO0 of the first RDRAM device on the

module.

Serial I/O. Pin for reading from and writing to the control reg-

isters. Attaches to SIO1 of the last RDRAM device on the

module.

SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1

and SA2.

Serial Presence Detect Write Protect (active high). When low,

the SPD can be written as well as read.

CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.

Supply voltage for the RDRAM core and interface logic.

Logic threshold reference voltage for RSL signals.

I/O

RSL

I/O

RSL

I/O

RSL

CMOS

SIN

B34

I/O

SOUT

A34

I/O

CMOS

SWP

CMOS

Vdd

Vref

A47

B47

A39, B39

A35, B35, A44, B44, A46, B46

A42, B42

Page 4

Rev. 1.0 May 2004

参数对比

与MS18R1624EH0-CT9相近的元器件有：MS18R1628EH0-CM8、MS18R1628EH0-CK8、MS18R1628EH0-CT9、MS18R1624EH0-CK8、MS18R1624EH0-CM8、MS18R1622EH0-CT9、MS18R1622EH0-CM8、MS18R1622EH0-CK8。描述及对比如下：

型号	MS18R1624EH0-CT9	MS18R1628EH0-CM8	MS18R1628EH0-CK8	MS18R1628EH0-CT9	MS18R1624EH0-CK8	MS18R1624EH0-CM8	MS18R1622EH0-CT9	MS18R1622EH0-CM8	MS18R1622EH0-CK8
描述	Rambus DRAM Module, 64MX18, 32ns, CMOS, SORIMM-160	Rambus DRAM Module, 128MX18, CMOS, SORIMM-160	Rambus DRAM Module, 128MX18, CMOS, SORIMM-160	Rambus DRAM Module, 128MX18, CMOS, SORIMM-160	Rambus DRAM Module, 64MX18, 45ns, CMOS, SORIMM-160	Rambus DRAM Module, 64MX18, 40ns, CMOS, SORIMM-160	Rambus DRAM Module, 32MX18, 32ns, CMOS, SORIMM-160	Rambus DRAM Module, 32MX18, 40ns, CMOS, SORIMM-160	Rambus DRAM Module, 32MX18, 45ns, CMOS, SORIMM-160
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	符合
厂商名称	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)
零件包装代码	DMA	DMA	DMA	DMA	DMA	DMA	DMA	DMA	DMA
包装说明	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25	DIMM, DIMM160,25
针数	160	160	160	160	160	160	160	160	160
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL	BLOCK ORIENTED PROTOCOL
其他特性	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH	SELF CONTAINED REFRESH
最大时钟频率 (fCLK)	1066 MHz	800 MHz	800 MHz	1066 MHz	800 MHz	800 MHz	1066 MHz	800 MHz	800 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160	R-XDMA-N160
内存密度	1207959552 bit	2415919104 bit	2415919104 bit	2415919104 bit	1207959552 bit	1207959552 bit	603979776 bit	603979776 bit	603979776 bit
内存集成电路类型	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE	RAMBUS DRAM MODULE
内存宽度	18	18	18	18	18	18	18	18	18
功能数量	1	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1	1
端子数量	160	160	160	160	160	160	160	160	160
字数	67108864 words	134217728 words	134217728 words	134217728 words	67108864 words	67108864 words	33554432 words	33554432 words	33554432 words
字数代码	64000000	128000000	128000000	128000000	64000000	64000000	32000000	32000000	32000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
组织	64MX18	128MX18	128MX18	128MX18	64MX18	64MX18	32MX18	32MX18	32MX18
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25	DIMM160,25
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V	1.8/2.5,2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V
最小供电电压 (Vsup)	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	NO	NO	NO	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.635 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
最长访问时间	32 ns	-	-	-	45 ns	40 ns	32 ns	40 ns	45 ns