PEDS82V32520-01
1
Semiconductor
MS82V32520
524,288-Word
×
32-Bit
×
2-Bank FIFO-SGRAM
This version:
Jul. 2001
Preliminary
GENERAL DESCRIPTION
The MS82V32520 is a 32-Mbit system clock synchronous dynamic random access memory. In addition to the
conventional random read/write access function, the MS82V32520 provides the automatic row address increment
function and automatic bank switching function. Therefore, if once the row and column addresses are set,
continuous serial accesses are possible while banks are automatically switched till input of the Precharge
command. The MS82V32520 is ideal for digital camera and TV buffer memory applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
524,288 words
×
32 bits
×
2 banks memory (2,048 rows
×
256 columns
×
32 bits
×
2 banks)
Single 3.3 V
±0.3
V power supply
LVTTL compatible inputs and outputs
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (2, 3)
Automatic row address increment function and automatic bank switching function
Power Down operation and Clock Suspend operation
4,096 refresh cycles/64 ms
Auto refresh and self refresh capability
Package:
86-pin 400 mil plastic TSOP (II) (TSOP (2) 86-P-400-0.50-K)
(Product : MS82V32520-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
MS82V32520-75
MS82V32520-8
MS82V32520-10
Max. Operating Frequency
133 MHz
125 MHz
100 MHz
Access Time
5.5 ns
6 ns
7 ns
86-pin Plastic TSOP (II) (400 mil)
Package
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PEDS82V32520-01
1
Semiconductor
MS82V32520
PIN CONFIGURATION (TOP VIEW)
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
WE
CAS
RAS
CS
NC
BA(A11)
NC
A10/AP
A0
A1
A2
DQM2
V
CC
NC
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
86-Pin Plastic TSOP (II)
(Type K)
Pin Name
A0 – A10
A0 – A7
BA(A11)
CLK
CKE
CS
RAS
CAS
Function
Row Address Inputs
Column Address Inputs
Bank Address
System Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Pin Name
WE
DQM0 – DQM3
DQ0 – DQ31
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write Enable
DQ Mask Enable
Data Inputs/outputs
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQ
No Connection
Note: The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
For the four-bank 64Mb SDRAM, Pin 22 = BA0 and Pin 23 = BA1, and for the two-bank 64Mb
SDRAM, Pin 22 = BA.
Therefore, when the MS82V32520 is used in place of a 64Mb SDRAM, care must be taken in
bank address control.
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PEDS82V32520-01
1
Semiconductor
MS82V32520
BLOCK DIAGRAM
CKE
CLK
CS
RAS
CAS
WE
DQM0
to
DQM3
I/O
Controller
Timing
Register
Bank
BA
Controller
Internal
Col.
Address
A0 to
A10
BA
Counter
Input
Data
Register
Input
Buffers
Column
32
32
8
8 Address
Buffers
Column
Decoders
Sense
Amplifiers
32
Read
Data
Register
32
Output
Buffers
32
DQ0
to
DQ31
Internal
Row
Address
Counter
Row
Decoders
Row
Word
Drivers
Word
Drivers
16Mb
Memory Cells
Bank A
16Mb
Memory Cells
Bank B
Row
Decoders
11
Address
Buffers
Sense
Amplifiers
8
Column
Decoders
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PEDS82V32520-01
1
Semiconductor
MS82V32520
PIN DESCRIPTION
CLK
CS
CKE
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA10
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA = “L”: Bank A
BA = “H”: Bank B
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.
Data inputs/outputs are multiplexed on the same pin.
Address
BA
RAS
CAS
WE
DQM0 –
DQM3
DQ0 – DQ31
*Notes: 1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,
DQM0, DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA.
BA
0
1
Active, read or write
Bank A
Bank B
3. The auto precharge function is enabled or disabled by the A10/AP input when the read or
write command is issued.
A10/AP
0
1
0
1
BA
0
0
1
1
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A10/AP
and BA inputs.
A10/AP
0
0
1
BA
0
1
×
Operation
Bank A is precharged.
Bank B is precharged.
Both banks A and B are precharged.
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PEDS82V32520-01
1
Semiconductor
MS82V32520
COMMAND OPERATION
Mode Register Set Command (CS
RAS CAS WE
= “Low”)
CS,
CS RAS, CAS,
The MS82V32520 has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst
Sequence”. The Mode Register Set command should be executed just after the MS82V32520 is powered on.
Before entering this command, all banks must be precharged. Next command can be issued after t
RSC
.
Auto Refresh Command (CS
RAS CAS
= “Low”,
WE
= “High”)
CS,
CS RAS,
The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be
performed 4,096 times within 64 ms and the next command can be issued after t
RC
from last Auto Refresh
command. Before entering this command, all banks must be precharged.
Self Refresh Entry/Exit Command (CS
RAS CAS CKE
= “Low”,
WE
= “High”)
CS,
CS RAS, CAS,
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”.
This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by
the internal address counter on the MS82V32520 chip.
In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be
precharged. Next command can be issued after t
RC
.
Single Bank Precharge Command (CS
RAS WE
A10/AP = “Low”,
CAS
= “High”)
CS,
CS RAS, WE,
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA.
All Banks Precharge Command (CS
RAS WE
= “Low”,
CAS
A10/AP = “High”)
CS,
CAS,
CS RAS,
The All Bank Precharge command triggers precharge of both of the banks A and B.
If this command is executed during special bank active mode, the special bank active mode is terminated.
Bank Active Command (CS
RAS
= “Low”,
CAS WE
= ”High”)
CS,
CAS,
CS
The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to
conventional DRAM's
RAS
falling operation. Row addresses “A0 – A10 and BA” are strobed.
Write Command (CS
CAS WE
A10/AP = “Low”,
RAS
= “High”)
CS,
CS CAS, WE,
The Write command is required to begin burst write operation. Then burst access initial bit column address is
strobed.
Write with Auto Precharge Command (CS
CAS WE
= “Low”,
RAS
A10/AP = “High”)
CS,
RAS,
CS CAS,
The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after
the burst write. Any command that interrupts this operation cannot be issued.
Read Command (CS
CAS
A10/AP = “Low”,
RAS WE
= “High”)
CS,
RAS,
CS CAS,
The Read command is required to begin burst read operation. Then burst access initial bit column address is
strobed.
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