Freescale Semiconductor
Data Sheet
Document Number: MSC8156E
Rev. 2, 5/2011
MSC8156E
Six-Core Digital Signal
Processor with Security
• Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache configurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit timers, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
• Chip-level arbitration and switching system (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other initiators and the M2 memory, shared M3 memory,
DDR SRAM controllers, device configuration control and status
registers, MAPLE-B, and other targets.
• 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can
be turned off to save power.
• 96 Kbyte boot ROM.
• Three input clocks (one global and two differential).
• Five PLLs (three global and two Serial RapidIO PLLs).
• Multi-Accelerator Platform Engine for Baseband (MAPLE-B)
with a programmable system interface, Turbo decoding, Viterbi
decoding, and FFT/iFFT and DFT/iDFT processing. MAPLE-B
can be disabled when not required to reduce overall power
consumption.
• Security Engine (SEC) optimized to process all the algorithms
associated with IPSec, IKE, SSL/TLS, 3GPP, and LTE using 4
crypto-channels with multi-command descriptor chains,
integrated controller for assignment of the eight execution units
(PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the
random number generator (RNG), and XOR engine to accelerate
parity checking for RAID storage applications.
• Two DDR controllers with up to a 400 MHz clock (800 MHz data
rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to
four banks (two per controller) and support for DDR2 and DDR3.
• DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channels with up to 1024 buffer descriptors
per channel, and programmable priority, buffer, and multiplexing
configuration. It is optimized for DDR SDRAM.
• Up to four independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 62.5 Mbps data rate for each TDM link, and with glueless
interface to E1 or T1 framers that can interface with
H-MVIP/H.110 devices, TSI, and codecs such as AC-97.
FC-PBGA–783
29 mm
×
29 mm
• High-speed serial interface that supports two Serial RapidIO
interfaces, one PCI Express interface, and two SGMII interfaces
(multiplexed). The Serial RapidIO interfaces support 1x/4x
operation up to 3.125 Gbaud with a single messaging unit and two
DMA units. The PCI Express controller supports 32- and 64-bit
addressing, x4, x2, and x1 link.
• QUICC Engine technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting two communication controllers for two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
• I/O Interrupt Concentrator consolidates all chip maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT, NMI_OUT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• Two general-purpose 32-bit timers for RTOS support per SC3850
core, four timer modules with four 16-bit fully programmable
timers, and eight software watchdog timers (SWT).
• Eight programmable hardware semaphores.
• Up to 32 virtual interrupts and a virtual NMI asserted by simple
write access.
• I
2
C interface.
• Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
• Boot interface options include Ethernet, Serial RapidIO interface,
I
2
C, and SPI.
• Supports standard JTAG interface
• Low power CMOS design, with low-power standby and
power-down modes, and optimized power-management circuitry.
• 45 nm SOI CMOS technology.
© 2008–2011 Freescale Semiconductor, Inc.
Table of Contents
1
2
Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagram. . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .24
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25
2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .25
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .36
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .53
3.1 Power Supply Ramp-Up Sequence . . . . . . . . . . . . . . .53
3.2 PLL Power Supply Design Considerations . . . . . . . . . .56
3.3 Clock and Timing Signal Board Layout Considerations 57
3.4 SGMII AC-Coupled Serial Link Connection Example . .57
3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .58
3.6 Guide to Selecting Connections for Remote Power
Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 39
Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 39
Figure 16.DDR2 and DDR3 SDRAM Differential Timing
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16.Differential Measurement Points for Rise and Fall Time 41
Figure 17.Single-Ended Measurement Points for Rise and Fall Time
Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 43
Figure 19.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 44
Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 23.Timer AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 47
Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 48
Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27.SPI AC Timing in Slave Mode (External Clock). . . . . . . 49
Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 50
Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 52
Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33.Supply Ramp-Up Sequence with V
DD
Ramping Before
V
DDIO
and CLKIN Starting With V
DDIO
. . . . . . . . . . . . . 53
Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 55
Figure 35.Reset Connection in Functional Application . . . . . . . . . 55
Figure 36.Reset Connection in Debugger Application. . . . . . . . . . 55
Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 42.4-Wire AC-Coupled SGMII Serial Link Connection
Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 40.MSC8156E Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3
4
5
6
7
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
MSC8156E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
StarCore SC3850 DSP Subsystem Block Diagram . . . . 3
MSC8156E FC-PBGA Package, Top View . . . . . . . . . . . 4
Differential Voltage Definitions for Transmitter or
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 29
Figure 6. SerDes Transmitter and Receiver Reference Circuits . 30
Figure 7. Differential Reference Clock Input DC Requirements
(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. Differential Reference Clock Input DC Requirements
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. Single-Ended Reference Clock Input DC Requirements 31
Figure 10.SGMII Transmitter DC Measurement Circuit . . . . . . . . 34
MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
2
Freescale Semiconductor
DDR Interface 64/32-bit
JTAG
DDR
Controller
DDR Interface 64/32-bit
DDR
Controller
M3 Memory
1056 Kbyte
I/O-Interrupt
Concentrator
UART
Clocks
CLASS
High-Speed Serial Interface
SC3850
DSP Core
32 Kbyte 32 Kbyte
L1
L1
ICache DCache
512 Kbyte
L2 Cache / M2 Memory
Timers
Reset
DMA
DMA
Semaphores
Virtual
Interrupts
Boot ROM
I
2
C
Other
Modules
4x 3.125 Gbaud
PCI-EX 1x/2x/4x
Two SGMII
4x 3.125 Gbaud
Two SGMII
MAPLE-B
DFT/
IDFT
FFT/
IFFT
Turbo/
Viterbi
QUICCEngine™
Subsystem
Dual RISC Processors
SPI Ethernet Ethernet
4 TDMs
SGMII
x2
Serial Serial
PCI
RMU
RapidIO RapidIO Expr
SEC
DMA
SerDes 1
SerDes 2
Six DSP Cores at 1 GHz
Four TDMs 256-Channels each
SPI RGMII RGMII
Note: The arrow direction indicates master or slave.
Figure 1. MSC8156E Block Diagram
128 bits master
bus to CLASS
128 bits slave
bus from CLASS
Interrupts
512 Kbyte L2 Cache / M2 Memory
EPIC
Timer
IQBus
TWB
DQBus
Task
Protection
Debug Support
OCE30 DPU
32 Kbyte
Instruction
Cache
Write-
Through
Buffer
(WTB)
32 Kbyte
Data
Cache
Write-
Back
Buffer
Address
Translation
MMU
(WBB)
SC3850
Core
P-bus 128 bit
Xa-bus 64 bit
Xb-bus 64-bit
Figure 2. StarCore SC3850 DSP Subsystem Block Diagram
MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
Freescale Semiconductor
3
Pin Assignment
1
Pin Assignment
This section includes diagrams of the MSC8156E package ball grid array layouts and tables showing how the pinouts are
allocated for the package.
1.1
FC-PBGA Ball Layout Diagram
The top view of the FC-PBGA package is shown in
Figure 3
with the ball location index numbers.
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MSC8156E
Figure 3. MSC8156E FC-PBGA Package, Top View
MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
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Freescale Semiconductor
1.2
Signal List By Ball Location
Table 1
presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is
appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the
related signal functions are used (active)
Note:
The information in
Table 1
and
Table 2
distinguishes among three concepts. First, the power pins are the balls of the
device package used to supply specific power levels for different device subsystems (as opposed to signals). Second,
the power rails are the electrical lines on the board that transfer power from the voltage regulators to the device. They
are indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as N/A
with regard to the power rails. Third, symbols used in these tables are the names for the voltage levels (absolute,
recommended, and so on) and not the power supplies themselves.
Table 1. Signal List by Ball Number
Ball Number
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
B1
B2
B3
B4
B5
B6
B7
B8
M2DQS3
M2DQS3
M2ECC0
M2DQS8
M2DQS8
M2A5
M2CK1
M2CK1
M2CS0
M2BA0
M2CAS
M2DQ34
M2DQS4
M2DQS4
M2DQ50
M2DQS6
M2DQS6
M2DQ48
M2DQ49
VSS
Reserved
SXPVDD1
SXPVSS1
Reserved
Reserved
SXCVDD1
SXCVSS1
M2DQ24
GVDD2
M2DQ25
VSS
GVDD2
M2ECC1
VSS
GVDD2
Signal Name
1,2
Pin Type
10
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
NC
Power
Ground
NC
NC
Power
Ground
I/O
Power
I/O
Ground
Power
I/O
Ground
Power
Power Rail
Name
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
GVDD2
N/A
—
N/A
N/A
—
—
N/A
N/A
GVDD2
N/A
GVDD2
N/A
N/A
GVDD2
N/A
N/A
MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
Freescale Semiconductor
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