E2G0016-17-41
¡ Semiconductor
MSM512100/L
¡ Semiconductor
This version: Jan. 1998
MSM512100/L
Previous version: May 1997
2,097,152-Word
¥
1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM512100/L is a 2,097,152-word
¥
1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM512100/L achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer
metal CMOS process. The MSM512100/L is available in a 26/20-pin plastic SOJ. The MSM512100L
(the low-power version) is specially designed for lower-power applications.
FEATURES
• 2,097,152-word
¥
1-bit configuration
• Single 5 V power supply,
±10%
tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Fast page mode, read modify write capability
•
CAS
before
RAS
refresh, hidden refresh,
RAS-only
refresh capability
• Multi-bit test mode capability
• Package:
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM512100/L-xxSJ)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM512100/L-60
MSM512100/L-70
MSM512100/L-80
Access Time (Max.)
t
RAC
t
AA
t
CAC
t
OEA
60 ns 30 ns 15 ns 15 ns
70 ns 35 ns 20 ns 20 ns
80 ns 40 ns 20 ns 20 ns
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
110 ns
130 ns
150 ns
440 mW
385 mW
330 mW
5.5 mW/
0.55 mW (L-version)
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¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
D
IN
1
WE
2
RAS
3
NC 4
A10R 5
A0 9
A1 10
A2 11
A3 12
V
CC
13
MSM512100/L
26 V
SS
25 D
OUT
24
CAS
23
OE
22 A9
18 A8
17 A7
16 A6
15 A5
14 A4
26/20-Pin Plastic SOJ
Pin Name
A0 - A9, A10R
RAS
CAS
D
IN
D
OUT
OE
WE
V
CC
V
SS
NC
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input
Data Output
Output Enable
Write Enable
Power Supply (5 V)
Ground (0 V)
No Connection
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¡ Semiconductor
MSM512100/L
BLOCK DIAGRAM
RAS
CAS
Timing
Generator
Timing
Generator
10
Column
Address
Buffers
10
Column
Decoders
Write
Clock
Generator
WE
OE
A0 - A9
Internal
Address
Counter
Refresh
Control Clock
Sense
Amplifiers
I/O
Selector
Output
Buffer
D
OUT
10
A10R
V
CC
1
Row
Address
Buffers
11
Row
De-
coders
Word
Drivers
Memory
Cells
Input
Buffer
D
IN
On Chip
V
BB
Generator
V
SS
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¡ Semiconductor
MSM512100/L
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
V
T
I
OS
P
D
*
T
opr
T
stg
Rating
–1.0 to 7.0
50
1
0 to 70
–55 to 150
Unit
V
mA
W
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min.
4.5
0
2.4
–1.0
Typ.
5.0
0
—
—
Max.
5.5
0
6.5
0.8
(Ta = 0°C to 70°C)
Unit
V
V
V
V
Capacitance
Parameter
Input Capacitance (A0 - A9, A10R, D
IN
)
Input Capacitance (RAS,
CAS, WE, OE)
Output Capacitance (D
OUT
)
Symbol
C
IN1
C
IN2
C
OUT
Typ.
—
—
—
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
Max.
6
7
7
Unit
pF
pF
pF
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¡ Semiconductor
DC Characteristics
MSM512100/L
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C)
Condition
MSM512100 MSM512100 MSM512100
/L-60
/L-70
/L-80
Unit Note
Min.
Max.
V
CC
0.4
10
Min.
2.4
0
–10
Max.
V
CC
0.4
10
Min.
2.4
0
–10
Max.
V
CC
0.4
10
V
V
mA
2.4
0
–10
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
V
OH
I
OH
= –5.0 mA
V
OL
I
OL
= 4.2 mA
0 V
£
V
I
£
6.5 V;
I
LI
All other pins not
under test = 0 V
D
OUT
disable
0 V
£
V
O
£
5.5 V
RAS, CAS
cycling,
t
RC
= Min.
RAS, CAS
= V
IH
I
CC2
RAS, CAS
≥
V
CC
–0.2 V
RAS
cycling,
I
CC3
CAS
= V
IH
,
t
RC
= Min.
RAS
= V
IH
,
I
CC5
CAS
= V
IL
,
D
OUT
= enable
I
CC6
RAS
cycling,
CAS
before
RAS
RAS
= V
IL
,
I
CC7
CAS
cycling,
t
PC
= Min.
t
RC
= 125
ms,
I
CC10
CAS
before
RAS,
t
RAS
£
1
ms
Output Leakage Current
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Average Power
Supply Current
(RAS-only Refresh)
Power Supply
Current (Standby)
Average Power
Supply Current
(CAS before
RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
I
LO
–10
10
–10
10
–10
10
mA
I
CC1
—
—
—
—
—
80
2
1
100
80
—
—
—
—
—
70
2
1
100
70
—
—
—
—
—
60
2
1
100
60
mA 1, 2
mA
mA
1
1, 5
mA 1, 2
—
5
—
5
—
5
mA
1
—
80
—
70
—
60
mA 1, 2
—
60
—
50
—
40
mA 1, 3
—
200
—
200
—
200
mA
1, 4,
5
Notes : 1.
2.
3.
4.
5.
I
CC
Max. is specified as I
CC
for output open condition.
The address can be changed once or less while
RAS
= V
IL
.
The address can be changed once or less while
CAS
= V
IH
.
V
CC
– 0.2 V
£
V
IH
£
6.5 V, –1.0 V
£
V
IL
£
0.2 V.
L-version.
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