E2G0149-29-41
¡ Semiconductor
MSM514102D/DL
¡ Semiconductor
This version: Apr. 1999
MSM514102D/DL
4,194,304-Word
¥
1-Bit DYNAMIC RAM : STATIC COLUMN MODE TYPE
DESCRIPTION
The MSM514102D/DL is a 4,194,304-word
¥
1-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514102D/DL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM514102D/DL is available in a 26/20-pin plastic SOJ, 20-
pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514102DL (the low-power version) is specially
designed for lower-power applications.
FEATURES
• 4,194,304-word
¥
1-bit configuration
• Single 5 V power supply,
±10%
tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Static Column mode, read modify write capability
•
CS
before
RAS
refresh, hidden refresh,
RAS-only
refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ
(SOJ26/20-P-300-1.27)
(Product : MSM514102D/DL-xxSJ)
20-pin 400 mil plastic ZIP
(ZIP20-P-400-1.27)
(Product : MSM514102D/DL-xxZS)
26/20-pin 300 mil plastic TSOP
(TSOPII26/20-P-300-1.27-K) (Product : MSM514102D/DL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM514102D/DL-60
MSM514102D/DL-70
MSM514102D/DL-80
Access Time (Max.)
t
RAC
60 ns
70 ns
80 ns
t
AA
30 ns
35 ns
40 ns
t
CAC
15 ns
20 ns
20 ns
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
110 ns
130 ns
150 ns
495 mW
440 mW
385 mW
5.5 mW/
1.1 mW (L-version)
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¡ Semiconductor
MSM514102D/DL
PIN CONFIGURATION (TOP VIEW)
D
IN
1
26 V
SS
24
CS
22 A9
18 A8
17 A7
16 A6
15 A5
14 A4
A9 1
WE
2
NC 4
25 D
OUT
23 NC
D
OUT
3
D
IN
5
NC 9
RAS
7
2
CS
D
IN
1
RAS
3
A10 5
A0 9
4 V
SS
6
WE
WE
2
NC 4
RAS
3
8 A10
A0 11
A2 13
A5 17
A7 19
10 NC
12 A1
14 A3
16 A4
18 A6
20 A8
A10 5
A0 9
A1 10
A2 11
A3 12
V
CC
15
A1 10
A2 11
A3 12
V
CC
13
V
CC
13
26/20-Pin Plastic SOJ
20-Pin Plastic ZIP
26/20-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A10
RAS
CS
D
IN
D
OUT
WE
V
CC
V
SS
NC
Function
Address Input
Row Address Strobe
Chip Select Input
Data Input
Data Output
Write Enable
Power Supply (5 V)
Ground (0 V)
No Connection
26 V
SS
24
CS
23 NC
22 A9
18 A8
17 A7
16 A6
15 A5
14 A4
25 D
OUT
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¡ Semiconductor
MSM514102D/DL
BLOCK DIAGRAM
RAS
CS
Timing
Generator
Timing
Generator
11
Column
Address
Buffers
11
Column
Decoders
Write
Clock
Generator
WE
A0 - A10
Internal
Address
Counter
Refresh
Control Clock
Sense
Amplifiers
I/O
Selector
Output
Buffer
D
OUT
11
Row
Address
Buffers
11
Row
De-
coders
Word
Drivers
Memory
Cells
Input
Buffer
D
IN
V
CC
On Chip
V
BB
Generator
V
SS
3/17
¡ Semiconductor
MSM514102D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
V
T
I
OS
P
D
*
T
opr
T
stg
Rating
–1.0 to 7.0
50
1
0 to 70
–55 to 150
Unit
V
mA
W
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min.
4.5
0
2.4
–1.0
Typ.
5.0
0
—
—
Max.
5.5
0
6.5
0.8
(Ta = 0°C to 70°C)
Unit
V
V
V
V
Capacitance
Parameter
Input Capacitance (A0 - A10, D
IN
)
Input Capacitance (RAS,
CS, WE)
Output Capacitance (D
OUT
)
Symbol
C
IN1
C
IN2
C
OUT
Typ.
—
—
—
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
Max.
6
7
7
Unit
pF
pF
pF
4/17
¡ Semiconductor
DC Characteristics
MSM514102D/DL
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Condition
MSM514102 MSM514102 MSM514102
D/DL-60
D/DL-70
D/DL-80
Unit Note
Min.
Max.
V
CC
0.4
10
Min.
2.4
0
–10
Max.
V
CC
0.4
10
Min.
2.4
0
–10
Max.
V
CC
0.4
10
V
V
mA
2.4
0
–10
V
OH
I
OH
= –5.0 mA
V
OL
I
OL
= 4.2 mA
0 V
£
V
I
£
6.5 V;
I
LI
All other pins not
under test = 0 V
D
OUT
disable
0 V
£
V
O
£
5.5 V
RAS, CS
cycling,
t
RC
= Min.
RAS, CS
= V
IH
I
CC2
RAS, CS
≥
V
CC
–0.2 V
RAS
cycling,
I
CC3
CS
= V
IH
,
t
RC
= Min.
RAS
= V
IH
,
I
CC5
CS
= V
IL
,
D
OUT
= enable
I
CC6
RAS
cycling,
CS
before
RAS
RAS
= V
IL
,
I
CC9
Address cycling,
t
SC
= Min.
t
RC
= 125
ms,
I
CC10
CS
before
RAS,
t
RAS
£
1
ms
Output Leakage Current
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Average Power
Supply Current
(RAS-only Refresh)
Power Supply
Current (Standby)
Average Power
Supply Current
(CS before
RAS
Refresh)
Average Power
Supply Current
(Static Column Mode)
Average Power
Supply Current
(Battery Backup)
I
LO
–10
10
–10
10
–10
10
mA
I
CC1
—
—
—
—
—
90
2
1
200
90
—
—
—
—
—
80
2
1
200
80
—
—
—
—
—
70
2
1
200
70
mA 1, 2
mA
mA
1
1, 5
mA 1, 2
—
5
—
5
—
5
mA
1
—
90
—
80
—
70
mA 1, 2
—
80
—
70
—
60
mA 1, 3
—
300
—
300
—
300
mA
1, 4,
5
Notes : 1.
2.
3.
4.
5.
I
CC
Max. is specified as I
CC
for output open condition.
The address can be changed once or less while
RAS
= V
IL
.
The address can be changed once or less while
CS
= V
IH
.
V
CC
– 0.2 V
£
V
IH
£
6.5 V, –1.0 V
£
V
IL
£
0.2 V.
L-version.
5/17
