Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
E2L0032-17-Y1
¡ Semiconductor
¡ Semiconductor
MSM518221
262,214-Word
¥
8-Bit Field Memory
This version: Jan. 1998
MSM518221
Previous version: Dec. 1996
DESCRIPTION
The OKI MSM518221 is a high performance 2-Mbit, 256K
¥
8-bit, Field Memory. It is designed for
high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies
and Multi-media systems. The 2-Mbit capacity fits one field of a conventional NTSC TV screen.
Each of the 8-bit planes has separate serial write and read ports. These employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also supported,
which allow alternate data rates between write and read data streams.
The MSM518221 provides high speed FIFO, First-In First-Out, operation without external refreshing:
it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing operations
are prevented by special arbitration logic.
The MSM518221's function is simple, and similar to a digital delay device whose delay-bit-length is
easily set by reset timing. The delay length, and the number of read delay clocks between write and
read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256
¥
8-bit enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
The MSM518221 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514221B.
It has a write mask function or input enable function (IE), and read-data skipping function or output
enable function (OE). The differences between write enable (WE) and input enable (IE), and between
read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously
applied to MSM518221. The input enable (IE) function allows the user to write into selected locations
of the memory only, leaving the rest of the memory contents unchanged. This facilitates data
processing to display a "picture in picture" on a TV screen.
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¡ Semiconductor
MSM518221
FEATURES
• Single power supply : 5 V
±10%
• 512 Rows
¥
512 Columns
¥
8 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access
Read/write cycle time
25 ns/30 ns/40 ns
Access time
25 ns/25 ns/30 ns
• Functional compatibility with OKI MSM514221B
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options :
28-pin 400 mil plastic ZIP
(ZIP28-P-400-1.27)
28-pin 400 mil plastic SOJ
(SOJ28-P-400-1.27)
28-pin 430 mil plastic SOP
(SOP28-P-430-1.27-K)
(Product : MSM518221-xxZS)
(Product : MSM518221-xxJS)
(Product : MSM518221-xxGS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM518221-25ZS
MSM518221-30ZS
MSM518221-40ZS
MSM518221-25JS
MSM518221-30JS
MSM518221-40JS
MSM518221-30GS-K
MSM518221-40GS-K
Access Time (Max.)
25 ns
25 ns
30 ns
25 ns
25 ns
30 ns
25 ns
30 ns
Cycle Time (Min.)
25 ns
30 ns
40 ns
25 ns
30 ns
40 ns
30 ns
40 ns
430 mil 28-pin SOP
400 mil 28-pin SOJ
400 mil 28-pin ZIP
Package
2/16
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
WE
D
IN
0
D
IN
2
V
CC
D
IN
5
1
3
5
7
9
2
4
6
8
IE
D
IN
1
D
IN
3
D
IN
4
10 D
IN
6
12 RSTW
14 NC
16 RE
18 D
OUT
7
20 D
OUT
5
22 V
SS
24 D
OUT
2
26 D
OUT
0
28 SRCK
D
IN
7 11
SWCK 13
NC 15
OE 17
D
OUT
6 19
D
OUT
4 21
D
OUT
3 23
D
OUT
1 25
RSTR 27
D
IN
4 1
D
IN
5 2
D
IN
6 3
D
IN
7 4
28 V
CC
D
IN
4 1
D
IN
5 2
D
IN
6 3
D
IN
7 4
27 D
IN
3
26 D
IN
2
25 D
IN
1
24 D
IN
0
23 IE
22 WE
21 NC
RSTW 5
NC 7
RE 8
OE 9
RSTW 5
SWCK 6
SWCK 6
NC 7
RE 8
OE 9
20 SRCK
19 RSTR
D
OUT
7 10
D
OUT
6 11
D
OUT
5 12
D
OUT
4 13
V
SS
14
D
OUT
7 10
D
OUT
6 11
D
OUT
5 12
D
OUT
4 13
V
SS
14
18 D
OUT
0
17 D
OUT
1
16 D
OUT
2
15 D
OUT
3
28-Pin Plastic SOJ
MSM518221
28 V
CC
27 D
IN
3
26 D
IN
2
25 D
IN
1
24 D
IN
0
23 IE
22 WE
21 NC
20 SRCK
19 RSTR
18 D
OUT
0
17 D
OUT
1
16 D
OUT
2
15 D
OUT
3
28-Pin Plastic SOP
28-Pin Plastic ZIP
Pin Name
SWCK
SRCK
WE
RE
IE
OE
RSTW
RSTR
D
IN
0 - 7
D
OUT
0 - 7
V
CC
V
SS
NC
Function
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply (5 V)
Ground (0 V)
No Connection
3/16
¡ Semiconductor
D
OUT
(¥ 8)
OE
RE
BLOCK DIAGRAM
RSTR
SRCK
Data-out
Buffer (¥ 8)
Serial
Read
Controller
512 Word Serial Read Register (¥ 8)
Read Line Buffer
Low-Half (¥ 8)
256 (¥ 8)
71 Word
Sub-Register (¥ 8)
256K (¥ 8)
Memory
Array
71 Word
Sub-Register (¥ 8)
256 (¥ 8)
Write Line Buffer
Low-Half (¥ 8)
256 (¥ 8)
Write Line Buffer
High-Half (¥ 8)
Clock
Oscillator
X
Decoder
Read/Write
and Refresh
Controller
Read Line Buffer
High-Half (¥ 8)
256 (¥ 8)
512 Word Serial Write Register (¥ 8)
V
BB
Generator
Data-in
Buffer (¥ 8)
MSM518221
Serial
Write
Controller
4/16
D
IN
(¥ 8)
IE
WE
RSTW
SWCK