E2G0128-17-61
¡ Semiconductor
MSM51V16805D/DSL
¡ Semiconductor
This version: Mar. 1998
MSM51V16805D/DSL
Pr
el
im
in
ar
y
2,097,152-Word
¥
8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V16805D/DSL is a 2,097,152-word
¥
8-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM51V16805D/DSL achieves high integration, high-speed operation,
and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
double-layer metal CMOS process. The MSM51V16805D/DSL is available in a 28-pin plastic SOJ or
28-pin plastic TSOP. The MSM51V16805DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 2,097,152-word
¥
8-bit configuration
• Single 3.3 V power supply,
±0.3
V tolerance
• Input
: LVTTL compatible, low input capacitance
• Output : LVTTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode with EDO, read modify write capability
•
CAS
before
RAS
refresh, hidden refresh,
RAS-only
refresh capability
•
CAS
before
RAS
self-refresh capability (SL version)
• Multi-bit test mode capability
• Package options:
28-pin 400 mil plastic SOJ
(SOJ28-P-400-1.27)
(Product : MSM51V16805D/DSL-xxJS)
28-pin 400 mil plastic TSOP
(TSOPII28-P-400-1.27-K) (Product : MSM51V16805D/DSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
t
RAC
t
AA
t
CAC
t
OEA
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
84 ns
104 ns
124 ns
360 mW
324 mW
288 mW
1.8 mW/
0.72 mW (SL version)
MSM51V16805D/DSL-50 50 ns 25 ns 13 ns 13 ns
MSM51V16805D/DSL-60 60 ns 30 ns 15 ns 15 ns
MSM51V16805D/DSL-70 70 ns 35 ns 20 ns 20 ns
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¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
V
CC
1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE
6
RAS
7
A11R 8
A10R 9
,
28 V
SS
V
CC
1
27 DQ8
DQ1 2
DQ2 3
DQ3 4
DQ4 5
26 DQ7
25 DQ6
24 DQ5
23
CAS
22
OE
WE
6
RAS
7
21 A9R
20 A8
19 A7
18 A6
17 A5
16 A4
15 V
SS
A11R 8
A10R 9
A0 10
A1 11
A2 12
A3 13
V
CC
14
28-Pin Plastic SOJ
A0 10
A1 11
A2 12
A3 13
V
CC
14
Pin Name
A0 - A8,
A9R - A11R
RAS
CAS
DQ1 - DQ8
OE
WE
V
CC
V
SS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
Write Enable
Power Supply (3.3 V)
Ground (0 V)
MSM51V16805D/DSL
28 V
SS
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23
CAS
22
OE
21 A9R
20 A8
19 A7
18 A6
17 A5
16 A4
15 V
SS
28-Pin Plastic TSOP
(K Type)
Note :
The same power supply voltage must be provided to every V
CC
pin, and the same GND
voltage level must be provided to every V
SS
pin.
2/17
¡ Semiconductor
MSM51V16805D/DSL
BLOCK DIAGRAM
WE
RAS
CAS
9
OE
I/O
Controller
Output
Buffers
8
Timing
Generator
8
DQ1 - DQ8
Column
Address
Buffers
Internal
Address
Counter
9
9
Column Decoders
8
Input
Buffers
8
A0 - A8
Refresh
Control Clock
Sense Amplifiers
8
I/O
Selector
8
A9R - A11R
3
Row
Row
Address
12
Deco-
Buffers
ders
Word
Drivers
Memory
Cells
V
CC
On Chip
V
BB
Generator
V
SS
3/17
¡ Semiconductor
MSM51V16805D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
V
T
I
OS
P
D
*
T
opr
T
stg
Rating
–0.5 to 4.6
50
1
0 to 70
–55 to 150
Unit
V
mA
W
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min.
3.0
0
2.0
–0.3
Typ.
3.3
0
—
—
Max.
3.6
0
V
CC
+ 0.3
0.8
(Ta = 0°C to 70°C)
Unit
V
V
V
V
Capacitance
Parameter
Input Capacitance
(A0 - A8, A9R - A11R)
Input Capacitance (RAS,
CAS, WE, OE)
Output Capacitance (DQ1 - DQ8)
Symbol
C
IN1
C
IN2
C
I/O
Typ.
—
—
—
(V
CC
= 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)
Max.
5
7
7
Unit
pF
pF
pF
4/17
¡ Semiconductor
DC Characteristics
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
MSM51V16805D/DSL
(V
CC
= 3.3 V ±0.3 V, Ta = 0°C to 70°C)
Condition
MSM51V16805 MSM51V16805 MSM51V16805
D/DSL-50
D/DSL-60
D/DSL-70 Unit Note
Min.
V
OH
I
OH
= –2.0 mA
V
OL
I
OL
= 2.0 mA
0 V
£
V
I
£
V
CC
+ 0.3 V;
I
LI
All other pins not
under test = 0 V
DQ disable
0 V
£
V
O
£
V
CC
RAS, CAS
cycling,
t
RC
= Min.
RAS, CAS
= V
IH
I
CC2
RAS, CAS
≥
V
CC
–0.2 V
RAS
cycling,
I
CC3
CAS
= V
IH
,
t
RC
= Min.
RAS
= V
IH
,
I
CC5
CAS
= V
IL
,
DQ = enable
I
CC6
RAS
cycling,
CAS
before
RAS
RAS
= V
IL
,
I
CC7
CAS
cycling,
t
HPC
= Min.
t
RC
= 31.3
ms,
I
CC10
CAS
before
RAS,
t
RAS
£
1
ms
RAS
£
0.2 V,
CAS
£
0.2 V
—
400
—
400
—
400
mA
1, 4,
5
—
100
—
90
—
80
mA
1, 3
—
75
—
70
—
65
mA
1, 2
—
5
—
5
—
5
mA
1
—
75
—
70
—
65
mA
1, 2
–10
10
–10
10
–10
10
mA
2.4
0
Max.
V
CC
0.4
Min.
2.4
0
Max.
V
CC
0.4
Min.
2.4
0
Max.
V
CC
0.4
V
V
Output Leakage Current
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Average Power
Supply Current
(RAS-only Refresh)
Power Supply
Current (Standby)
Average Power
Supply Current
(CAS before
RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
Average Power
Supply Current
(CAS before
RAS
Self-Refresh)
I
LO
–10
10
–10
10
–10
10
mA
I
CC1
—
—
—
—
75
2
0.5
200
—
—
—
—
70
2
0.5
200
—
—
—
—
65
2
0.5
200
mA
1, 2
mA
mA
1
1, 5
I
CCS
—
300
—
300
—
300
mA
1, 5
Notes : 1.
2.
3.
4.
5.
I
CC
Max. is specified as I
CC
for output open condition.
The address can be changed once or less while
RAS
= V
IL
.
The address can be changed once or less while
CAS
= V
IH
.
V
CC
– 0.2 V
£
V
IH
£
V
CC
+ 0.3 V, –0.3 V
£
V
IL
£
0.2 V.
SL version.
5/17
安防电子
