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MSM56V16160J-8T3-K

描述:
Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-50
分类:
存储    存储   
文件大小:
309KB,共34页
制造商:
概述
Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-50
器件参数
参数名称
属性值
厂商名称
LAPIS Semiconductor Co Ltd
零件包装代码
TSOP2
包装说明
SOP, TSOP50,.46,32
针数
50
Reach Compliance Code
unknown
ECCN代码
EAR99
访问模式
DUAL BANK PAGE BURST
最长访问时间
6 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
125 MHz
I/O 类型
COMMON
交错的突发长度
1,2,4,8
JESD-30 代码
R-PDSO-G50
内存密度
16777216 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
16
功能数量
1
端口数量
1
端子数量
50
字数
1048576 words
字数代码
1000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
1MX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装等效代码
TSOP50,.46,32
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
电源
3.3 V
认证状态
Not Qualified
刷新周期
4096
自我刷新
YES
连续突发长度
1,2,4,8,FP
最大待机电流
0.002 A
最大压摆率
0.12 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
GULL WING
端子节距
0.8 mm
端子位置
DUAL
文档预览
OKI Semiconductor
MSM56V16160J
2-Bank
×
524,288-Word
×
16-Bit SYNCHRONOUS DYNAMIC RAM
FEDD56V16160J-07
Issue Date: Oct. 26, 2005
DESCRIPTION
The MSM56V16160J is a 2-Bank
×
524,288-word
×
16-bit Synchronous dynamic RAM. The device
operates at 3.3V. The inputs and outputs are LVTTL compatible.
FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
• 2-Bank
×
524,288-word
×
16-bit configuration
Single 3.3 V power supply,
±0.3
V tolerance
Input : LVTTL compatible
Output : LVTTL compatible
Refresh : 4096 cycles/64 ms
Programmable data transfer mode
-
CAS
Latency (2, 3)
- Burst Length (1, 2, 4, 8, Full Page)
- Data scramble (sequential, interleave)
Auto-refresh, Self-refresh capability
• Packages:
50-pin 400mil plastic TSOP(TypeII) (TSOPII50-P-400-0.80-K) (Product:MSM56V16160J-xxTS-K)
(Product:MSM56V16160J-xxT3-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Max.
Frequency
133MHz
125MHz
100MHz
Access Time (Max.)
t
AC2
5.4ns
6ns
6ns
t
AC3
5.4ns
6ns
6ns
MSM56V16160J-75
MSM56V16160J-8
MSM56V16160J-10
1/34
FEDD56V16160J-07
OKI Semiconductor
MSM56V16160J
PIN CONFIGURATION (TOP VIEW)
V
CC
DQ1
DQ2
V
SS
Q
1
2
3
4
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ16
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
DQ3 5
DQ4 6
V
CC
Q 7
DQ5 8
DQ6 9
V
SS
Q 10
DQ7 11
DQ8 12
V
CC
Q 13
LDQM 14
WE 15
CAS 16
RAS 17
CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
V
CC
25
50-Pin Plastic TSOP (II)
(K Type)
Pin Name
CLK
CS
CKE
A0–A10
A11
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
UDQM, LDQM
DQi
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Data Input / Output Mask
Data Input / Output
Power Supply (3.3V)
Ground (0V)
Data Output Power Supply (3.3V)
Data Output Ground (0V)
No Connection
Note : The same power supply voltage must be provided to every V
CC
pin .
The same power supply voltage must be provided to every V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
2/34
FEDD56V16160J-07
OKI Semiconductor
MSM56V16160J
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the “H” edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address
: RA0 – RA10
Column Address
: CA0 – CA7
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B
CKE
Address
A11
RAS
CAS
WE
UDQM,
LDQM
DQi
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the
clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H”
edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.
Data inputs/outputs are multiplexed on the same pin.
3/34
FEDD56V16160J-07
OKI Semiconductor
MSM56V16160J
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to V
SS
V
CC
Supply Voltage
Storage Temperature
Power Dissipation
Short Circuit Output Current
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
, V
CC
Q
T
stg
P
D*
I
OS
T
opr
Value
–0.5 to V
CC
+ 0.5
–0.5 to 4.6
–55 to 150
1000
50
0 to 70
Unit
V
V
°C
mW
mA
°C
*: Ta = 25°C
Recommended Operating Conditions
(Voltages referenced to V
SS
= 0 V)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
, V
CC
Q
V
IH
V
IL
Min.
3.0
2.0
−0.3
Typ.
3.3
Max.
3.6
V
CC
+ 0.3
0.8
Unit
V
V
V
Pin Capacitance
(V
bias
= 1.4 V, Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (CLK)
Input Capacitance (CKE, A0 – A11,
CS,
RAS, CAS, WE,
UDQM, LDQM )
Input/Output Capacitance (DQ1 – DQ16)
Symbol
C
CLK
C
IN
C
OUT
Min.
Max.
4
5
6.5
Unit
pF
pF
pF
4/34
FEDD56V16160J-07
OKI Semiconductor
MSM56V16160J
DC Characteristics (1/2)
MSM56V16160J
Condition
Parameter
Symbol
-75
-8
Max.
0.4
10
10
Min.
2.4
−10
−10
Max.
0.4
10
10
Unit
Note
Bank
Output High
Voltage
Output Low
Voltage
Input Leakage
Current
Output Leakage
Current
Average Power
Supply Current
(Operating)
Power Supply
Current
(Standby)
Average Power
Supply Current
(Clock
Suspension)
Average Power
Supply Current
(Active Standby)
Power Supply
Current (Burst)
Power Supply
Current
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
Average Power
Supply Current
(Power Down)
V
OH
V
OL
I
LI
I
LO
CKE
Others
I
OH
=−2.0mA
I
OL
=2.0mA
t
CC
= Min.
t
RC
= Min.
No Burst
t
CC
= Min.
Min.
2.4
−10
−10
V
V
µA
µA
One Bank
CKE≥V
IH
I
CC1
Active
Both
I
CC2
Banks
CKE≥V
IH
Precharge
Both
I
CC3S
Banks
Active
90
80
mA
1,2
35
35
mA
3
CKE≤V
IL
t
CC
= Min.
3
3
mA
2
I
CC3
One Bank
CKE≥V
IH
Active
t
CC
= Min.
40
40
mA
3
Both
I
CC4
Banks
Active
I
CC5
CKE≥V
IH
t
CC
= Min.
130
120
mA
1,2
One Bank
CKE≥V
IH
Active
t
CC
= Min.
t
RC
= Min.
130
120
mA
2
Both
CKE≤V
IL
I
CC6
Banks
Precharge
Both
CKE≤V
IL
I
CC7
Banks
Precharge
t
CC
= Min.
2
2
mA
t
CC
= Min.
2
2
mA
5/34
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