Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
¡ Semiconductor
MSM58321
¡ Semiconductor
REAL TIME CLOCK/CALENDAR
DESCRIPTION
The MSM 58321 is a metal gate CMOS Real
Time Clock/Calendar with a battery backup
function for use in bus-oriented micropro-
cessor applications.
The 4-bit bidirectional bus line method is used
for the data I/O circuit; the clock is set, cor-
rected, or read by accessing the memory.
MSM58321
The time is read with 4-bit DATA I/O, AD-
DRESS WRITE, READ, and
BUSY;
it is written
with 4-bit DATA I/O, ADDRESS WRITE,
WRITE, and
BUSY.
FEATURES
• 7 Function-Second, Minute, Hour, Day,
Day-of-Week, Month, Year
• Automatic leap year calender
• 12/24 hour format
• Frequency divider 5-poststage reset
• Reference signal output
32.768 kHz crystal controlled operation
Single 5V power supply
Back-up battery operation to V
DD
= 2.2V
Low power dissipation
90
µW
max. at V
DD
= 3V
2.5 mW max. at V
DD
= 5V
• 16 pin plastic DIP (DIP 16-P-300)
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
5-poststage (O
11
~O
15
)
XT
XT
BUSY
N
STOP
R
p
TEST
R
p
WRITE
R
p
READ
R
p
CS1
R
p
CS2
R
p
D0
D1
D2
D3
TRI-STATE
CONTROL
ADDRESS
LATCH
ADDRESS
DECODER
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E-F
S1
S10
MI1
MI10
H1
H10
W
D1
D10
MO1
MO10
Y1
Y10
D
E-F
1024 Hz
1 Hz
1/60 Hz
1/3600 Hz
\DATA BUS
4
E-F
4
SWITCH
S1 S10
1/10 1/6
3
4
MI1 MI10
1/10 1/6
MINUTE
3
H1 H10
1/12 or 1/24
W
1/7
WEEK
RFB
1
OSC
2
15
R
BUSY
R
4
3
TEST
D
WRIETE
1 Hz
WRITE
S1 S10
MI1 MI10
H1 H10
W
SECOND
HOUR
READ
CS
4
D1 D10
1/10 1/3
DAY
WRITE
D1
D10
MO1 MO10
Y1
Y10
DATA BUS
TEST-P
4
4
MO1 MO10
4
Y1 Y10
1/10 1/10
YEAR
4
1/12
MONTH
R
p
= 200 k TYP
ADDRESS
WRITE
R
p
7
MSM58321
PIN CONFIGURATION
16 pin Plastic DIP (top View)
CS
2
1
16 V
DD
15 XT
14
XT
13 CS
1
12 TEST
11 STOP
10
BUSY
¡ Semiconductor
WRITE 2
READ
D
0
D
1
D
2
D
3
GND
3
4
5
6
7
8
9 ADDRESS WRITE
REGISTER TABLE
Address input
Address
D
0
(A
0
)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
1
(A
1
)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D
2
(A
2
)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
D
3
(A
3
)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Register
Name
D
0
S
1
S
10
MI
1
MI
10
H
1
H
10
W
D
1
D
10
MO
1
MO
10
Y
1
Y
10
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Data input/
output
Count value
D
1
D
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D
3
*
0
0
0
0
0
to
to
to
to
to
9
5
9
5
9
Remarks
0
1
2
3
4
5
6
7
8
9
A
B
C
D
D2 = 1 specifies PM, D2 = 0 specifies AM, D3 = 1 specifies 24-hour timer, and
0~1 or 0~2 D3 = 0 specifies 12-hour timer.
When D3 = 1 is written, the D2 bit is reset inside the IC.
0
0
0
0
0
0
0
to
to
to
to
to
to
to
6
9
3
9
1
9
9
The D2 and D3 bits in D10 are used to select a leap year.
Remainder obtained by dividing the
Calendar
D
2
D
3
year number by 4
Gregorian calendar 0 0
0
1 0
3
0 1
2
1 1
1
A selector to reset 5 poststages in the 1/2
15
frequency divider and the BUSY
circuit. They are reset when this code is latched with ADDRESS LATCH and
the WRITE input goes to 1.
A selector to obtain reference signal output. Reference signals are output to
D0 – D3 when this code is latched with ADDRESS LATCH and READ input
goes to 1.
E~F
0/1
1
1
1
Note:
(1)
(2)
(3)
There are no bits in blank fields for data input/output. 0 signals are output by reading and data is
not stored by writing because there are no bits.
The bit with marked * is used to select the 12/24-hour timer and the bits marked * are
used to select a leap year. These three bits can be read or written.
When signals are input to bus lines D0 – D3 and ADDRESS WRITE goes to 1 for address input,
ADDRESS information is latched with ADDRESS LATCH.
8
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Power voltage
Input voltage
Output voltage
Storage temperature
Symbol
V
DD
V
I
V
O
T
stg
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
–
Value
MSM58321
Unit
V
V
V
°C
–0.3 to 6.5
–0.3 to V
DD
+0.3
–0.3 to V
DD
+0.3
–55 to +150
Operating Conditions
Rating
Power voltage
Date hold voltage
Crystal frequency
Operating temperature
Note:
Symbol
V
DD
V
DH
ƒ(XT)
T
OP
Condition
–
–
–
–
Value
4.5 to 6
2.2 to 6
32.768
–30 to +85
Unit
V
V
kHz
°C
The data hold voltage guarantees the clock operations, though it does not guarantee operations outside
the IC and data input/output.
DC Characteristics
(V
DD
= 5V ±5%, Ta = –30 ~ +85°C)
Rating
H input voltage
L input voltage
L output voltage
L output current
H input current
L input current
Input capacity
Current consumption
Note:
Symbol
V
IH1
V
IH2
V
IL
V
OL
I
OL
I
IH1
I
IH2
I
IL
C
I
I
DD
Condition
– Note 1
– Note 2
–
I
O
= 1.6 mA
V
O
= 0.4 V
V
I
= V
DD
Note3
V
I
= V
DD
Note4
V
I
= 0V
ƒ = 1 MHz
ƒ = 32.768 kHz
V
DD
= 5V/V
DD
= 3V
Min.
3.6
V
DD
–0.5
–
–
1.6
10
–
–
–
–
Typ.
–
–
–
–
–
30
–
–
5
100/15
Max.
–
–
0.8
0.4
–
80
1
–1
–
500/30
µA
pF
µA
Unit
V
V
V
mA
µA
1.
2.
3.
4.
CS
2
, WRITE, READ, ADDRESS WRITE, STOP, TEST, D
0
~ D
3
CS
1
CS
1
, CS
2
, WRITE, READ, ADDRESS WRITE, STOP, TEST
D
0
~ D
3
9
MSM58321
Switching Characteristics
(1) WRITE mode
¡ Semiconductor
(V
DD
= 5V ±5%, Ta = 25°C)
Rating
CS setup time
CS hold time
Address setup time
Address write pulse width
Address hold time
Data setup time
Write pulse width
Data hold time
Symbol
t
CS
t
CH
t
AS
t
AW
t
AH
t
DS
t
WW
t
DH
Condition
–
–
–
–
–
–
–
–
Min.
0
0
0
0.5
0.1
0
2
0
Typ.
–
–
–
–
–
–
–
–
Max.
–
–
–
–
–
–
–
–
Unit
µs
µs
µs
µs
µs
µs
µs
µs
CS1
CS2
D0 ~ D3
(ADDRESS/DATA)
ADDRESS WRITE
,,
,
H
L
,,
,,
,,
,,
t
CS
t
AS
t
AW
t
AH
t
DS
t
WW
t
DH
t
CH
,,
,,
,,
High
,
Impedance
,,
,
,
,,
,,
WRITE
,,
IC internal
ADDRESS
IC internal DATA
ADDRESS
DATA
Write Cycle
Note:
ADDRESS WRITE and WRITE inputs are activated by the level, not by the edge.
10
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