E2E0010-38-94
¡ Semiconductor
MSM6351/6351L
¡ Semiconductor
This version: Sep. 1998
MSM6351/6351L
Previous version: Mar. 1996
Built-in 8 or 5 bit Serial Port and LCD Driver 4-Bit Microcontroller
GENERAL DESCRIPTION
The MSM6351/6351L is a low-power microcontroller manufactured in silicon gate CMOS
technology. Integrated into a single chip are ROM, RAM, five I/O ports, serial I/O port, time-
base counter, LCD driver, three interrupts, crystal oscillator, and voltage tripler.
The MSM6351/6351L, which can drive LCD display with higher-count segments, is best suited
to battery powered applications, such as watches and game machines.
The built-in 8-bit or 5-bit serial port provides a data communication capability with external
machines.
FEATURES
• Low power consumption
• Large capacity memory
• ROM
: 4096 words
¥
15 bits
• RAM
: 1024 words
¥
4 bits
• I/O port
Input-output port
: 5 ports
¥
4 bits (input or output can be specified for each port)
• 62 LCD drivers (1/3 duty or 1/4 duty is selectable. Up to 232 segments can be displayed)
• Single 1.5 V power supply operation (MSM6351)
Can be changed to 3.0 V specification by mask option (MSM6351L).
• Melody function
• Built-in watchdog timer
• Built-in 8-bit or 5-bit serial port (asynchronous or synchronous selectable)
• 32.768 kHz crystal oscillator
• Package options:
100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name :MSM6351-¥¥GS-K/
MSM6351L-¥¥GS-K)
100-pin plastic QFP (QFP100-P-1420-0.65-L) (Product name :MSM6351-¥¥GS-L/
MSM6351L-¥¥GS-L)
100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name :MSM6351-¥¥GS-BK/
MSM6351L-¥¥GS-BK)
Chip
¥¥
indicates a code number.
1/17
¡ Semiconductor
BLOCK DIAGRAM
SIN
SOUT
SCLK
A-Bus
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
XTOUT
XT
XT
RESET
TEST1
TEST2
TEST3
P03C
P02C
P01C
P00C
D-Bus
SBFF u
SBFF l
SERIAL
I/O
SCNT SCND
ACC
S-Bus
PORT0
PORT1
PORT2
PORT3
PORT4
FLAG
ALU
BANK
P4¥C
WDOG0
P3¥C
WDOG1
P2¥C
P2.0 to P23
P1¥C
EIRT IRQRT IEXM0 IEXM1 IEXM2
WATCH-
DOG
TIMER
INTERRUPT CONTROL
IRQEX
DATA
RAM
1024¥4Bits
PAGE
V
DD
FRMT
WORK
PROGRAM COUNTER(PC)
TIME BASE COUNTER
CAP1
CAP0
CAPF
TMOUT
PROGRAM
ROM
4096¥15Bits
ADDER
INSTRUCTION
REGISTER
MPX
MDTL MDTH
MELODY
BD
OSC
SYSTEM
CLOCK
GENERATOR
TEMP0
STACK
INSTRUCTION
DECODER
LCD DRIVER
VOLTAGE
REGURATOR
CONVERTER
SEG0
SEG1
SEG2
SEG3
SEG61
MSM6351/6351L
LCD CT
V
CP
V
CM
V
SS1
V
SS2
V
SS3
V
EE
2/17
¡ Semiconductor
MSM6351/6351L
PIN CONFIGURATION (TOP VIEW)
TEST3
TEST2
TEST1
RESET
P4.3
P4.2
P4.1
P4.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P0.3
P0.2
P0.1
P0.0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG30
P1.3
P1.2
P1.1
P1.0
BD
XTOUT
XT
XT
V
DD
V
SS3
V
SS2
V
SS1
V
EE
V
CP
V
CM
SOUT
SIN
SCLK
SEG31
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100-Pin Plastic QFP
3/17
¡ Semiconductor
MSM6351/6351L
PIN DESCRIPTIONS
Symbol
P0.0
P0.1
P0.2
P0.3
P1.0 to P1.3
P2.0
P2.1
P2.2
P2.3
P3.0 to P3.3
P4.0 to P4.3
PORT3
PORT4
• 4-bit I/O port 3
• 4-bit I/O port 4
I/O
PORT2
• 4-bit I/O port 2
PORT1
PORT0
Type
Description
• 4-bit I/O port 0
The input (*) /output, the existence (*) /
absence of pull-down resistance, and the
HALT function release enable/disable (*)
condition can be selected for each bit.
• 4-bit I/O port 1
The input (*) /output, External
the existence (*) /
interrupt
absence of pull-down signal
resistance, and the
HALT function
release enable/
disable (*) condition
can be selected for
each port.
A
Capture
trigger
signal
I/O Circuitry
• Oscillator clock output.
XTOUT
XT
XT
RESET
TEST1
TEST2
TEST3
SIN
SOUT
I
O
I
O
O
I
I
The oscillator clock is output when XTF (bit 3 of port P00C) is set
to "1".
• Oscillator connection pins.
• Reset input.
This is an input with a pull-down resistor. The system is reset when
"1" is input.
• Test input.
This is an input with a pull-down resistor.
• Serial port data input.
• Serial port data output. When the port is not in an output state,
this pin is set at high-impedance level, except when HZOUT
(bit 3 of port P2XC) =1 and transmitting data.
• Serial port clock input/output.
SCLK
I/O
The input/output (*) is switched by the serial port control register
SCNT. In the output mode, the serial clock frequency can be selected
from the demultiplied signal (1/1, 1/2 or 1/4 of the system clock).
BD
O
• Melody output (buzzer drive output).
• LCD drive output with 1/3 bias and 1/3 duty, or 1/3 bias and 1/4 duty.
The duty can be switched by LCD control register LCDCNT.
SEG0 to SEG61
O
A maximum of 177 segments can be displayed when using 1/3 duty
and 232 when using 1/4 duty.
—
I
H
G
D
F
C
B
E
*
Means system reset conditions.
4/17
¡ Semiconductor
MSM6351/6351L
PIN DESCRIPTIONS (continued)
Symbol
V
DD
V
SS1
V
SS2
V
SS3
V
EE
V
CM
V
CP
• 0 V power supply pin
• –1.5 V power supply pin (for 1.5 V operation)
• –3.0 V power supply pin (for 3.0 V operation)
• –4.5 V power supply pin
• Internal logic power supply pin
• Internal voltage converter capacitor connecting pin
Description
I/O Circuitry
—
—
—
—
—
—
Circuitry on Input/Output Pins
A. Input/output port
3-state CMOS buffer
I/O
CMOS inverter
Note:
V
SS
:
V
SS
10 kW
(Standard)
V
SS
1.5 V operationÆV
SS1
3.0 V operationÆV
SS2
Output enable
Pull-down enable
V
SS
B. Oscillator
I
XT
V
DD
O
XT
a
c
V
EE
V
EE
Note
a
c
V
DD
b
b
5/17
电源技术