E2U0014-28-81
¡ Semiconductor
MSM7541/7542
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
MSM7541/7542
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7541 and MSM7542 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in digital wireless systems.
The MSM7541 and MSM7542 use newly designed operational amplifiers to maintain small
current deviations caused by power voltage fluctuations.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type, directly drives a piezoelectric type
handset receiver.
FEATURES
• Single power supply: +3.0 V to +3.8 V
• Low power consumption
Operating mode:
23 mW Typ.
V
DD
= 3.3 V
Power save mode:
1 mW Typ.
V
DD
= 3.3 V
Power down mode:
0.04 mW Typ.
V
DD
= 3.3 V
• ITU-T Companding law
MSM7541:
m-law
MSM7542:
A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Built-in analog loop back test mode
• Differential type analog output. Directly drives a piezoelectric type receiver equivalent to 1.2
kW + 55 nF
• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7541RS)
(Product name : MSM7542RS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7541GS-K)
(Product name : MSM7542GS-K)
26-pin plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product name : MSM7541TS-K)
(Product name : MSM7542TS-K)
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¡ Semiconductor
MSM7541/7542
BLOCK DIAGRAM
AIN+
AIN–
+
–
RC
Active
BPF
(8th)
AD
Conv.
Auto
Zero
Transmit
Controller
PCMOUT
XSYNC
BCLOCK
GSX
TMC
PLL
R–TIM
VFRO
–
+
SG
SG
PWI
AOUT–
–
+
–
+
SG
SG
AOUT+
SG
Voltage
Ref.
Signal
Ground
SGC
SG
LPF
(5th)
Power
Down
DA
Conv.
PWD
Logic
Receive
Controller
RSYNC
PCMIN
PDN
V
DD
AG
DG
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¡ Semiconductor
MSM7541/7542
PIN CONFIGURATION (TOP VIEW)
SG 1
AOUT+ 2
AOUT– 3
PWI 4
VFRO 5
V
DD
6
DG 7
PDN 8
RSYNC 9
PCMIN 10
20 SGC
19 AIN+
18 AIN–
17 GSX
16 TMC
15 NC
14 AG
SG 1
AOUT+ 2
AOUT– 3
NC 4
PWI 5
VFRO 6
NC 7
V
DD
8
DG 9
PDN 10
RSYNC 11
24 SGC
23 AIN+
22 AIN–
21 GSX
20 NC
19 TMC
18 NC
17 NC
16 AG
15 BCLOCK
14 XSYNC
SG 1
AOUT+ 2
AOUT– 3
PWI 4
VFRO 5
26 SGC
25 AIN+
24 AIN–
23 GSX
22 TMC
V
DD
9
DG 10
PDN 11
18 NC
17 AG
16 BCLOCK
15 XSYNC
14 PCMOUT
13 BCLOCK PCMIN 12
12 XSYNC
11 PCMOUT
RSYNC 12
13 PCMOUT
PCMIN 13
NC : No connect pin
24-Pin Plastic SOP
NC : No connect pin
26-Pin Plastic TSOP
NC : No connect pin
20-Pin Plastic Skinny DIP
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¡ Semiconductor
MSM7541/7542
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
C1
Analog input
R1
GSX
AIN–
AIN+
SG
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1)
Gain = R2/R1
£
10
R2
–
+
2) Non inverting input type
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5)
Gain = 1 + R4 / R3
£
10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.0 V
PP
above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, the output signal of AOUT+ and AOUT– is available.
To apply the output signal of AOUT+ and AOUT– for driving, connect a resistor of 20 kW or more
between the pins VFRO and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of AG.
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¡ Semiconductor
PWI, AOUT+, AOUT–
MSM7541/7542
PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drives of an impedance of
1.2 kW + 55 nF, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example.
VI
Receive Filter
VFRO
PWI
R6
R7
R6 > 20 kW
ZL
≥
2.4 kW
Gain = VO/VI = 2
¥
R7/R6
£
2
SG
–
+
AOUT–
VO
ZL
SG
–
+
AOUT+
During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.
The electrical driving capability of the AOUT– pin and AOUT+ pin is
±1.3
V maximum. The
output load resistor has a minimum value of 1.2 kW.
If an output amplitude less than
±1.3
V is allowed, these outputs can drive a load resistance less
than that described above.
For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE.
V
DD
Power supply for +3.0 V to +3.8 V. (Typically 3.3 V)
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLOCK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
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