Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
E2F0008-28-63
¡ Semiconductor
MSM7661
¡ Semiconductor
NTSC/PAL Digital Video Decoder
This version: Jun. 1998
MSM7661
Previous version: Mar. 1998
Pr
el
im
in
ar
y
GENERAL DESCRIPTION
The MSM7661 is an LSI device which converts digitally sampled NTSC or PAL video signals to
8-bit digital data based on ITU-RBT601.
The input video signals available are composite video signals and S video signals.
The composite video signals are converted to YUV data via a 2-dimensional Y/C separation
circuit.
The A-to-D converted data is data sampled at pixel clock frequency or double pixel clock
frequency (the built-in decimation filter is used). Input signal synchronization can lock
synchronization and color burst at high speed through internal digital processing.
FEATURES (• indicates a new feature compared with MSM7660)
• Input video signals include the following two types of digital data that are A-to-D converted
at pixel frequency or double pixel frequency :
NTSC/PAL composite video signal
NTSC/PAL S video signal
°
8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601)
YCbCr
4:2:2
YCbC 4 : 1 : 1
• 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video
signal input)
NTSC: 3 lines/2 lines
PAL: 2 lines (3 virtual lines)
• Input signal synchronization can lock synchronization and color burst at high speed through
internal digital processing.
°
Sampling frequency
13.5 MHz (ITU-R601)
12.27 MHz (NTSC Square Pixel)
14.31818 MHz (NTSC 4Fsc)
14.75 MHz (PAL Square Pixel)
• Internal AGC/ACC circuit
Switchable between AGC and MGC (fixed gain)
• Built-in decimation filter located in the input stage allows easy configuration of an external
filter circuit (located ahead of A/D converter).
• Automatic NTSC/PAL recognition (only for ITU-RBT.601)
• Sleep mode
• Multiplex signal recognition (Teletext)
Data during vertical blanking is output in 8 bits in Through mode.
°
I
2
C-bus interface
• 3.3 V single power supply (each I/O pin is 5 V tolerable)
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7661GS-BK)
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BLOCK DIAGRAM
¡ Semiconductor
SYNC
(CSYNC_L)
PLLSEL
CLKX2O
CLKSEL
SYSSEL
HSY
VSYNC_L
HSYNC_L
VVALID
ODD
CLKX2
CLKXO
HVALID
VCO_CP
Synchronization Block
Y[7:0]
YD[7:0]
Decimation
Filter
lum.
Prologue Block
Luminance Block
(AGC + LPF)
Epilogue
Block
(2Dim. Y/C separate)
CD[7:0]
Decimation
Filter
Line Memory
(1kbyte)
¥
2
chr.
Chrominance Block
(ACC + LPF)
MODE[3:0]
C[7:0]
I
2
C-bus Control Logic
Test Control Logic
(Output Formatter)
MSM7661
SCL
SDA
RESET_L
TE
TEST1
TEST2
(SLEEP)
2/41
¡ Semiconductor
MSM7661
PIN CONFIGURATION (TOP VIEW)
56 CLKXO
55 HSYNC_L
54 VSYNC_L
53 HVALID
60 SYNC
59 VCO_CP
58 CLKX2O
57 SYSSEL
52 VVALID
51 ODD
62 CLKX2
61 HSY
64 V
DD
63 GND
CD[0] 1
CD[1] 2
CD[2] 3
CD[3] 4
CD[4] 5
CD[5] 6
CD[6] 7
CD[7] 8
CVBS[0] 9
CVBS[1] 10
CVBS[2] 11
CVBS[3] 12
CVBS[4] 13
CVBS[5] 14
CVBS[6] 15
CVBS[7] 16
V
DD
17
GND 18
SCL 19
SDA 20
MODE[0] 21
MODE[1] 22
MODE[2] 23
MODE[3] 24
50 GND
49 V
DD
48 C[0]
47 C[1]
46 C[2]
45 C[3]
44 C[4]
43 C[5]
42 C[6]
41 C[7]
40 Y[0]
39 Y[1]
38 Y[2]
37 Y[3]
36 Y[4]
35 Y[5]
34 Y[6]
33 Y[7]
RESET_L 25
PLLSEL 26
CLKSEL 27
TEST1 28
SLEEP 29
TE 30
64-Pin Plastic QFP
GND 31
V
DD
32
3/41
¡ Semiconductor
MSM7661
PIN DESCRIPTIONS
Pin
1 to 8
9 to 16
17
18
19
20
21 to 24
Symbol
CD[0 to 7]
CVBS[0 to 7]
V
DD
GND
SCL
SDA
MODE[0 to 3]
I
I/O
I
I
2
C-bus clock pin
I
2
C-bus data pin
Mode input pins. These pins are internally pulled-down.
MODE[3]
MODE[1:0]
0: composite
1: S video
00: ITU-R601
01: Square Pixel
10: 4Fsc (only for NTSC)
11: none
If ITU-R signals are input when registers are set to automatic NTSC/PAL
recognition mode, NTSC/PAL is automatically recognized irrespective of
MODE2 setting.
25
26
27
28
29
30
31
32
RESET_L
PLLSEL
CLKSEL
TEST1
SLEEP
TE
GND
V
DD
I
I
I
I
I
I
System reset pin (active at "L")
Unused.
Fixed to "H" externally.
Clock select input pin.
"L"
Æ
double-speed 27 MHz, "H"
Æ
ordinary 13.5 MHz
Input pin for testing. Normally "L". Internally pulled down.
Sleep mode setting pin. Normally "L". Internally pulled down.
Input pin for testing. Normally "L". Internally pulled down.
MODE[2]
0: NTSC
1: PAL
Type
I
I
Description
Chrominance signal input pin (valid only for S video input)
Set each pin to "L" level at composite signal input.
Composite signal input pin
Luminance signal is input for S video input.
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