Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
PEDL7662-02
PEDL7662-02
This version: Oct. 1999
MSM7662
Previous version : Oct. 1998
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¡ Semiconductor
MSM7662
¡ Semiconductor
NTSC/PAL Digital Video Decoder
GENERAL DESCRIPTION
The MSM7662 is an LSI device that decodes NTSC or PAL analog video signals into YCbCr and
RGB digital data based on ITU-RBT.601.
The device has built-in two channels of A/D converters and can accept composite video and S
video signals for the input video signals. Composite video signals are converted to YCbCr and
RGB digital data via the 2-dimensional Y/C separation circuit with an adaptive filter.
Analog video signals can be sampled by a clock at the pixel frequency or at twice the pixel
frequency. A decimation filter is built-in for sampling at twice the pixel frequency.
Input signals are synchronized internally and high-speed locking for color burst is possible.
Because a FIFO buffer is built into the output format circuit, jitter-free output can be obtained
even for non-standard signals.
APPLICATION EXAMPLES
Since the synchronization of input signals and high-speed locking for color burst are possible, the
device is optimized for applications used by switching multiple cameras.
It is also used for various image processing applications because of jitter-free output data
through a built-in FIFO buffer.
8-bit (YCbCr), 16-bit (8-bit (Y) + 8-bit (CbCr)), and 24-bit (RGB) output interfaces can be selected
as an output mode so that various devices such as monitoring system, digital video memory,
digital TV, video processing unit and video communication unit can be selected on the receiving
side.
FEATURES (• new feature not found on MSM7661B)
• Input analog signal
NTSC/PAL composite video signal or S-video signal
• Maximum 5 composite or 2 S-video + 2 composite analog inputs can be connected (switchable
by external pins or internal registers)
• Built-in clamp circuits and video amps
• Built-in 8-bit A/D converters (2 channels)
• 4 selectable output interfaces
ITU-RBT.656 (conditional)
8-bit (YCbCr)
: 8-bit (YCbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit)
16-bit (YCbCr) : 8-bit (Y) + 8-bit (CbCr) YCbCr = 4 : 2 : 2/YCbCr = 4 : 1 : 1 (limit)
24-bit RGB
: 8-bit (R) + 8-bit (G) + 8-bit (B)
°
2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S-video
signal input)
NTSC format: 3 lines or 2 lines, PAL format: 2 lines (3 virtual lines)
• Selectable data I/O signal synchronization
4 synchronization modes, internal FIFO modes (FIFO-1, FIFO-2) and external field memory
modes (FM-1, FM-2), are selectable (FIFO-1 is normally selected).
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PEDL7662-02
¡ Semiconductor
MSM7662
13.5 MHz (13.5/27 MHz)
: NTSC/PAL ITU-RBT.601
12.272727 MHz (12.272727/24.545454 MHz) : NTSC Square pixel
14.31818 MHz (14.31818/28.63636 MHz)
: NTSC 4fsc
14.75 MHz (14.75/29.5 MHz)
: PAL Square Pixel
• Built-in AGC/ACC circuits, compatible with a wide range of input levels
Input level range: –8 dB to +3.5 dB (0.4 V to 1.5 V)
Switchable between AGC/MGC (fixed gain) and ACC/MCC (fixed gain)
°
Decimation filter built into input stage, allows easy configuration of filter prior to A/D
converter (when input at twice the pixel frequency)
°
Automatic NTSC/PAL recognition (only for ITU-RBT.601)
°
Sleep mode
°
Multiplex signal recognition (closed caption)
During vertical blanking interval, data is output as 8-bit data.
°
I
2
C-bus interface
°
3.3 V single power supply (I/O 5 V tolerance)
°
Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7662TB)
°
Compatible pixel frequencies (normal/twice the pixel frequency)
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BLOCK DIAGRAM
¡ Semiconductor
CLKX2O
INS[2:0] GAINS[2:0]
CLKXO
CLKX2
CLKSEL
PLLSEL
VSYNC_L
HVALID
VVALID
STATUS1
STATUS3
HSYNC_L
ODD/EVEN
STATUS2
Synchronization Block
VRT2
ADIN2
AMPOUT2
CLPOUT2
VRB2
VIN6
VIN5
SW Matrix
M[7:4]
M[2:1]
ANALOG
AGC&
AMP
Decimation
Filter
Decimation
Filter
C ADC
Prologue Block
Luminance Block
DIGITAL
(AGC or MGC + LPF)
Epilogue
Block
(2 Dim. Y/C separate)
Y ADC
Line Memory
(1 KB)
¥
2
Chrominance Block
(ACC or MCC + LPF)
ITU-656
&
8 bits
(YCbCr)
Y[7:0]
(G[7:0])
VIN4
VIN3
VIN2
VIN1
VRB1
CLPOUT1
AMPOUT1
ADIN1
VRCL1
VRT1
ANALOG
AGC&
AMP
I
2
C-bus Control Logic
Test Control Logic
Output
Formatter
8 bits (Y)
8 bits (CbCr)
C[7:0]
(R[7:0])
8 bits (R)
8 bits (G)
8 bits (B)
B[7:0]
PEDL7662-02
MSM7662
3/62
MODE[3:0]
SCL
SDA
RESET_L
SLEEP
SCAN
TEST[2:0]
PEDL7662-02
,
¡ Semiconductor
96 GAINS[0]
95 GAINS[1]
94 GAINS[2]
100 DAGND
99 INS[0]
98 INS[1]
97 INS[2]
92 DGND
93 DV
DD
DAV
DD
VRT2
VIN6
VIN5
1
2
3
4
5
6
7
8
9
AD
DD
AGND
ADIN2
AMPOUT2
CLPOUT2
VRB2 10
AGND 11
AGND 12
VRB1 13
CLPOUT1 14
AMPOUT1 15
ADIN1 16
VRCL1 17
AGND 18
AV
DD
19
VIN4 20
VIN3 21
VIN2 22
VIN1 23
VRT1 24
DAV
DD
25
MSM7662
PIN CONFIGURATION (TOP VIEW)
83 STATUS1
82 STATUS2
81 STATUS3
77 CLKX2O
76 CLKXO
75 HSYNC_L
74 VSYNC_L
73 VVALID
72 HVALID
71 ODD/EVEN
70 C[0]
69 C[1]
68 C[2]
67 C[3]
66 C[4]
65 C[5]
64 C[6]
63 C[7]
62 DGND
61 DV
DD
60 Y[0]
59 Y[1]
58 Y[2]
57 Y[3]
56 Y[4]
55 Y[5]
54 Y[6]
53 Y[7]
52 DV
DD
51 DGND
80 CLKX2
B[4] 46
DAGND 26
MODE[0] 27
MODE[1] 28
MODE[2] 29
MODE[3] 30
SCAN 31
TEST[2] 32
TEST[1] 33
TEST[0] 34
SLEEP 35
RESET_L 36
DV
DD
37
DGND 38
SCL 39
SDA 40
PLLSEL 41
CLKSEL 42
B[7] 43
B[6] 44
B[5] 45
B[3] 47
B[2] 48
78 DGND
79 DV
DD
91 M[0]
90 M[1]
89 M[2]
88 M[3]
87 M[4]
86 M[5]
85 M[6]
84 M[7]
B[1] 49
100-Pin Plastic TQFP
B[0] 50
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嵌入式系统