Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
E2E1022-27-Y4
¡ Semiconductor
MSM80C48/49/50
MSM80C35/39/40
¡ Semiconductor
CMOS 8-Bit Microcontroller
This
MSM80C35/39/40
MSM80C48/49/50,
version: Jan. 1998
Previous version: Nov. 1996
GENERAL DESCRIPTION
The OKI MSM80C48/MSM80C49/MSM80C50 are 8-bit, low-power, high-performance micro-
controllers implemented in silicon-gate complementary metal-oxide semiconductor technology.
Integrated within these chips are 8K/16K/32K bits of mask program ROM, 512/1024/2048 bits
of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program memory and data
paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction
set, thereby optimizing power down, port data transfer, decrement and port float functions.
Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages QFP (GSK).
FEATURES
• Lower power consumption enabled by CMOS silicon gate process
• Completely static operation
• Improved power-down feature
• Instruction cycle
: 1.36
ms
(11 MHz) V
CC
=4.5 to 6.0 V (MSM80C48/49)
2.5
ms
(6 MHz) V
CC
=3.5 to 6.0 V (MSM80C50)
• 111 instructions
• All instructions are usable even during execution of external ROM instructions.
• Operation facility
Addition, logical operations, and decimal adjust
• Program memory (ROM)
: 1K words
¥
8 bits (MSM80C48)
: 2K words
¥
8 bits (MSM80C49)
: 4K words
¥
8 bits (MSM80C50)
• Data memory (RAM)
: 64 words
¥
8 bits (MSM80C48)
: 128 words
¥
8 bits (MSM80C49)
: 256 words
¥
8 bits (MSM80C50)
• Two sets of working registers
• External and timer interrupts
• Two test inputs
• Built-in 8-bit timer counter
• Extendable external memory and I/O ports
• I/O port
Input-output port
: 2 ports
¥
8 bits
Data bus input-output port
: 1 port
¥
8 bits
• Single-step execution function
• Wide range of operating voltage, from + 2.5 V to + 6 V of V
CC
• High noise margin action
• Compatible with Intel's 8048, 8049 and 8050
• Package
40-pin plastic DIP (DIP40-P-600-2.54)
: (MSM80C48-¥¥¥RS)
(MSM80C49-¥¥¥RS)
(MSM80C50-¥¥¥RS)
(MSM80C35RS)
(MSM80C39RS)
(MSM80C40RS)
44-pin plastic QFP(QFP44-P-910-0.80-2K) : (MSM80C48-¥¥¥GS-2K)
(MSM80C49-¥¥¥GS-2K)
(MSM80C50-¥¥¥GS-2K)
(MSM80C35GS-2K)
(MSM80C39GS-2K)
(MSM80C40GS-2K)
¥¥¥
indicates the code number.
1/20
(PORT 2)
8
PORT2 BUS BUFFER
2 or 3
BLOCK DIAGRAM
PORT2 LATCH
(LOW4) AND
EXPANDER
PORT I/O
PORT2
LATCH
(HIGH4)
8
HIGHER PROGRAM
COUNTER (4)
4
PROGRAM MEMORY
(ROM)
1K¥8bits MSM80C48RS
2K¥8bits MSM80C49RS
4K¥8bits MSM80C50RS
INSTRUC-
TION
REGISTER
PLA
¡ Semiconductor
4
4
OSC FREQ
∏480
TEST1
TIMER/EVENT
COUNTER (8)
LOWER PROGRAM
COUNTER
(8)
BUS LATCH
AND LOW
PC TEMP
REGISTER
BUS
BUFFER
8
(DATA
BUS
PORT)
(8)
ACCUMULATOR
(8)
RAM ADDRESS
REGISTER
TEMP REG (8)
INT
FLAG0
FLAG1
TIMER FLAG
CARRY
ACC
ACC Bit TEST
FLAGS
TEST0
TEST1
MULTIPLEXER
ACCUMULATOR
LATCH
(8)
ARITHMETIC
LOGIC
UNIT
(8)
CONDI-
TIONAL
BRANCH
LOGIC
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
DECODER
8-LEVEL
STACK
OPTIONAL
SECOND
REGISTER
BANK
DATA STORE
DECIMAL
ADJUST
PORT1
BUS
BUFFER
AND
LATCH
8
(PORT 1)
CONTROL AND TIMING
ALE
READ
STROBE
WRITE
STROBE
INT
RESET
PROG
EA
XTAL1 XTAL2
PSEN
SS
RD
WR
DATA MEMORY (RAM)
64¥8 bits MSM80C48RS
128¥8 bits MSM80C49RS
256¥8 bits MSM80C50RS
MSM80C48/49/50, MSM80C35/39/40
INTERRUPT
OSCILLATOR
PROM/
PROGRAM
XTAL
EXPANDER
MEMORY
STROBE
ENABLE
ADDRESS LATCH,
SINGLE
INITIALIZE
CPU MEMORY
DATA LATCH
STEP
SEPARATE
STROBE CYCLE
CLOCK
2/20
¡ Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN CONFIGURATION (TOP VIEW)
37 DB
7
36 DB
6
35 DB
5
XTAL1
XTAL2
RESET
SS
INT
EA
RD
PSEN
WR
ALE
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T1
P2
7
P2
6
P2
5
P2
4
P1
7
P1
6
P1
5
P1
4
P1
3
P1
2
P1
1
P1
0
V
DD
PROG
P2
3
P2
2
P2
1
P2
0
V
DD
P1
0
P1
1
P1
2
P1
3
P1
4
P1
5
NC
P1
6
1
2
3
4
5
6
7
8
9
34 DB
4
33 DB
3
32 DB
2
31 DB
1
30 DB
0
29 ALE
28
WR
27
PSEN
26
RD
25 EA
24
INT
23
SS
42 P2
3
41 P2
2
40 P2
1
T1 16
39 P2
0
V
CC
17
DB
0
12
DB
1
13
DB
2
14
DB
3
15
DB
4
16
DB
5
17
DB
6
18
DB
7
19
V
SS
20
P1
7
10
P2
4
11
NC 12
P2
5
13
P2
6
14
P2
7
15
T0 18
38 V
SS
44 NC
T0
1
40
V
CC
43 PROG
XTAL1 19
XTAL2 20
NC 21
NC: No-connection pin
40-Pin Plastic DIP
44-Pin Plastic QFP
RESET
22
3/20
¡ Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN DESCRIPTIONS
Symbol
P1
0
-P1
7
(PORT 1)
P2
0
-P2
7
(PORT 2)
Type
I/O
I/O
Description
8-bit quasi-bidirectional port
8-bit quasi-bidirectional port
The high-order four bits of external program memory addresses can be output
from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected.
Bidirectional port
The low-order eight bits of external program memory address can be output
from this port, and the addressed instruction is fetched under the control of
PSEN
signal. Also, the external data memory address is output, and data is
read and written synchronously using
RD
and
WR
signals.
The port can also serve as either a statically latched output port or a
non-latching input port.
The input can be tested with the conditional jump instructions JT0 and JNT0.
The execution of the ENT0 CLK instruction causes a clock output.
DB
0
-DB
7
(BUS)
I/O
T0
(Test 0)
I/O
T1
(Test 1)
INT
(Interrupt)
I
The input can be tested with the conditional jump instructions JT1 and JNT1.
The execution of a STRT CNT instruction causes an internal counter input.
Interrupt input. If interrupt is enabled,
INT
input initiates an interrupt.
Interrupt is disabled after a reset.
Also testable with a JNI instruction. Can be used to terminate the power-down
mode. (Active "0" level)
A signal to read data from external data memory. (Active "0" level)
A signal to write data to external data memory. (Active "0" level)
This signal is generated in each cycle. It may be used as a clock output.
External data memory or external program memory is addressed upon the
falling edge. For the external ROM, this signal is used to latch the bus port data
upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction.
A signal to fetch an instruction from external program memory
(Active "0" level)
RESET
input initialize the processor. (Active "0" level)
Used to terminate the power-down mode.
A program is executed step by step. This pin can also be used to control
internal oscillation when the power-down mode is reset.
(Active "0" level)
When held at high level, all instructions are fetched from external memory.
(Active "1" level)
This output strobes the MSM82C43RS I/O expander.
I
RD
(Read)
WR
(Write)
ALE
Address &
Data Latch
Clock
PSEN
Program
Store Enable
RESET
SS
(Single Step)
O
O
O
O
I
I
EA
(External Access)
PROG
(Expander Strobe)
I
O
4/20
