MT1020A
Bluetooth™ Baseband Controller
Product Brief
Features
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•
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•
•
•
•
•
Bluetooth
v1.1 compliant Link Controller
Programmable Radio Interface including BlueRF
Full
Bluetooth
Protocol Stack up to HCI
Full Duplex Audio CODEC including filtering
Linear PCM to log PCM and CVSD conversion
Advanced Block Power Management
Embedded ARM7TDMI™ Microcontroller Core
Configurable l/O supply 1.8 to 3.6V
1.8V internal supply option for Low Power
IP Hardware and Software available for
embedded applications
Single CPU
Bluetooth
system capability
PB5630
ISSUE 2.0
October 2001
Ordering Information
MT1020A/IG/BP1N 121-pin SSBGA
based microcontroller with on-chip memory, a full
duplex voice CODEC and a dedicated
Bluetooth
Baseband Peripheral (BBP) block.
The BBP implements all the time-critical elements of
Bluetooth
communication in hardware, with minimal
involvement by the microcontroller. Relieving the on-
chip processor of these repetitive tasks makes it
possible for the MT1020A to run entire applications
without an external host processor. A UART
Interface is provided for use when operation with an
an external host processor is required.
Comprehensive power management maximises
battery life for portable applications making the
MT1020A particularly suitable for low power
applications, especially those involving voice traffic.
Applications
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•
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Wireless Headsets
Wireless Accessories
Cellular Phones
Automotive
PDA, Laptop Computers
Digital Cameras
Absolute Maximum Ratings
Supply voltage (VDD )
Input voltage
Output voltage
Static discharge (HBM)*
Storage temperature, TSTG
-0.5V to +5V
-0.5V to OpV
DD
+0.5V
-0.5V to OpV
DD
+0.5V
2kV
-55˚C to +150˚C
* Human Body Model
Description
The MT1020A is a complete
Bluetooth
baseband
processor It combines an advanced ARM7TDMI
Figure 1 - MT1020A Block Diagram
1
MT1020A
Preliminary Information
11 10 9 8 7 6 5 4 3 2 1
A1 CORNER IDENT
A
B
C
D
E
F
G
H
J
K
L
TOP VIEW
BOTTOM VIEW
Figure 2 - Pin Connections
Pin
(see notes)
Signal Name
I/O Type
Qty
Description
Memory/Peripheral Interface
SADD[18:0]
A8: A9: C8:
D3: E4:
G10: G8:
G9: H10:
H4: H9: J1:
J2: J4: K1:
K2: K4: L3:
L4
C9: F7: B9:
C6: B1: C7:
D4: D7: F9:
D8: B8: E7:
D6: C3: C2:
B7
B6: E6
A1
K3: L2
B5
D2
F10
F3
E3
F4
E2
C5
O(hd)
19
System Address
SDATA[15:0]
I/O(hd)
16
System Data Bus
NSCS[1:0]
NSCS[3]
NSWE[1:0]
NSOE
NSUB
SWAIT
UART1
U1RXD
U1TXD
U1RTS
U1CTS
Host Interfaces
HST_UART_RXD
O(hd)
O(hd)
O(hd)
O(hd)
O
I(pd)
I(hd)
O
O
I(hd)
I(hd)
2
1
2
1
1
1
1
1
1
1
1
Active low System Chip Select 1 and 0
Active low System Chip Select 3
Active low System Write Enable 1 and 0
Active low System output enable
Active low System Upper Byte (for 16-bit
RAM)(SADD[0] = lower byte)
System Wait. Extended MPC access
UART1 Receive Data
UART1 Transmit Data
UART1 Ready to Send (active low
1
)
UART1 Clear to Send (active low
1
)
Serial Host Interface Receive Data
Table 1 - Pin Descriptions
2
Preliminary Information
Signal Name
HST_UART_TXD
HST_UART_RTS
HST_UART_CTS
Reserved
Reserved
Serial I/O
BSIO_SS
BSIO_DATA_O
BSIO_DATA_I
BSIO_CLK
General Purpose IO
GPIO[7]
EXTINT[2]
GPIO[6]
EXTINT[1]
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
INTNSCS0
GPIO[1]
BBPWAKE
GPIO[0]
Mode Control
NICE
NTRST
TEST
NSRESET
Diagnostics
TCK
BDIAG[0]
TDI
BDIAG[1]
TDO
BDIAG[2]
TMS
BDIAG[3]
H3
I/O
1
G4
O
1
H2
I/O
1
G5
I/O
1
ICE Test clock input or
Xdiag[0] output
ICE Test data input or
Xdiag[1] output
ICE Test data output or
Xdiag[2] output
ICE Scan test mode input or
Xdiag[3] output
J9
J3
H8
H11
I(pu)
I(pu)
I(pd)
I
1
1
1
1
C11
I/O(hd)
1
D9
I/O(hd)
1
E10
E9
E8
D10
I/O(hd)
I/O(hd)
I/O(hd)
I/O(hd)
1
1
1
1
F6
I/O(hd)
1
F8
I/O(hd)
1
General purpose I/O plus
External interrupt 2 input
General purpose I/O plus
External interrupt 1 input
General purpose I/O plus
General purpose I/O plus
General purpose I/O plus
General purpose I/O
C10
B11
B10
A11
O
O
I(hd)
O
1
1
1
1
Serial I/O Block Slave Select
Serial I/O Block Data Output
Serial I/O Block Data Input
Serial I/O Block Clock Output
Pin
(see notes)
D5
C4
A3
A2
B3
I/O Type
O
O
I/O(hd)
I/O
I/O
Qty
1
1
1
1
1
Description
MT1020A
Serial Host Interface Transmit Data
Serial Host Interface Ready to Send
Serial Host Interface Clear to Send
Tie to OPVDD
Tie to GND
During reset input selects int/ext NSCS0
General purpose I/O plus
Optional external BBP wake up input
General purpose I/O
Diagnostic or ICE mode ('0' = ICE mode)
Xpins/diag. Mode or ICE reset
Test enable
DO NOT CONNECT
System reset
Table 1 - Pin Descriptions (continued)
3
MT1020A
Signal Name
Radio Interface
RI_SYS_CLK
RI_CTR3
RI_TXDRXD
RI_RXD
RI_NRESET
RI_CTR2
RI_NSEN
RI_SBBO
RI_SBBI
RI_SCLK
RI_CTR1
RI_CTR0
Preliminary Information
Pin
(see notes)
I/O Type
Qty
Description
L7
J7
G6
L5
K8
G7
H7
L6
J6
H6
H5
J5
F2
F5
G3
G2
J11
J10
L9
K9
K10
I
I/O
I/O(hd)
I
I/O(pu)
I/O
O
I/O
I
O
I/O(pd)
O
I(hd)
O
I/O(hd)
I/O(hd)
AO
AO
AI
AI
AO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
System Clock Input
Bi-directional Radio Interface Control Signal 3
Radio Transmit Data Output.
(Receive Data input in Bi-Di pin mode)
Radio Receive Data Input
(Uni-directional pin mode)
Radio Reset
Bi-directional radio interface control signal 2
Active low radio serial interface enable
Radio Serial Transfer Data Output
Radio Serial Transfer Data Input
Radio Serial Transfer Clock
Bi-directional Radio Interface Control Signal 1
Bi-directional Radio Interface Control Signal 0
16bit Linear PCM Input stream
16bit Linear PCM Output stream
16bit Linear PCM Frame Sync Master / Slave
16bit Linear PCM Clock Master / Slave
Earpiece audio positive differential output
Earpiece audio negative differential output
Microphone audio negative differential input
Microphone audio positive differential input
Audio CODEC Vref decoupling capacitor pin;
100nF to AGND
Linear PCM Interface
LIN_PCM_IN
LIN_PCM_OUT
LIN_PCM_FRM
LIN_PCM_CLK
CODEC Interface
EAR_PLUS
EAR_MINUS
MIC_MINUS
MIC_PLUS
VREF
PLL Analogue Test
PLL_AT1
Power Supplies
GNDP
VDDP
GND
L11
K11
A6: B2: D1:
D11: F1:
G11: K6
L8
1
1
7
CODEC Output amplifier ground
CODEC Output amplifier VDD
Common Ground
E5
1
Phase Lock Loop 1 Analogue Test Pin
DO NOT CONNECT
VDDA
1
CODEC Analog VDD
Table 1 - Pin Descriptions (continued)
4
Preliminary Information
Signal Name
SUBGND
OPVDD
RIVDD
LAVDD
PLL_VDD
Pin
(see notes)
A4: A10: J8:
L1: L10
A7: C1: F11:
H1
K5
A5: E1: E11:
G1: K7
B4
I/O Type
Qty
5
4
1
5
1
Analog Ground
System I/O VDD
Radio Interface VDD
Core VDD
Phase Lock Loop VDD
Description
MT1020A
Note:
The UART CTS and RTS signals(U1RTS, U1CTS, HST_UART_RTS & HST_UART_CTS) are all active low at
the chip, but become active high after passing through a RS232 line driver IC.
Key
I
O
I/O
pu
pd
hd
to Signal Types:
input
Output
Bidirectional
Internal Pull-up
Internal Pull-down
Internal Peripheral HOLD cell: holds the previous voltage level of an input, until the weak drive of the hold
cell is overdriven by normal drive output. This can be either as part of a MT1020A bi-directional peripheral
cell or an external device.
Table 1 - Pin Descriptions (continued)
5
