256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100- and PC133-compliant, 144-pin, small-
outline, dual in-line memory module (SODIMM)
• Utilizes 100 MHz and 133 MHz SDRAM components
• Unbuffered
• 256MB (32 Meg x 64) and 512MB (64 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge and auto refresh modes
• Self refresh mode: standard and low-power
• 256MB module: 64ms, 4,096-cycle refresh (15.625µs
refresh interval); 512MB: 64ms, 8,192-cycle refresh
(7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge connectors
MT16LSDF3264(L)H – 256MB
MT16LSDF6464(L)H – 512MB
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 144-Pin SODIMM (MO-190)
PCB height: 1.25in (31.75mm)
Options
• Self refresh current
Standard
Low power
• Package
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
• Memory Clock/CL
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
• PCB
Height 1.25in (31.75mm)
NOTE:
Marking
None
L
1
G
Y
1
-13E
-133
-10E
See page 2 note
Table 1:
Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE
CLOCK
MARKING FREQUENCY CL = 2 CL = 3
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
–
6ns
–
5.4ns
–
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
1. Contact Micron for product availability.
Table 2:
Address Table
256MB
512MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
2 (S0#, S1#))
4K
4 (BA0, BA1)
128Mb (16 Meg x 8)
4K (A0–A11)
1K (A0–A9)
2 (S0#, S1#)
Refresh count
Device banks
Device configuration
Row addressing
Column addressing
Module ranks
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
1
©2006 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 3:
Part Numbers
MODULE DENSITY
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
SYSTEM
BUS SPEED
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
PART NUMBER
MT16LSDF3264(L)HG-13E_
MT16LSDF3264(L)HY-13E_
MT16LSDF3264(L)HG-133_
MT16LSDF3264(L)HY-133_
MT16LSDF3264(L)HG-10E_
MT16LSDF3264(L)HY-10E_
MT16LSDF6464(L)HG-13E_
MT16LSDF6464(L)HY-13E_
MT16LSDF6464(L)HG-133_
MT16LSDF6464(L)HY-133_
MT16LSDF6464(L)HG-10E_
MT16LSDF6464(L)HY-10E_
NOTE:
1. The designators for component and PCB revision are the last two characters of each part number Consult factory for
current revision codes. Example: MT16LSDF32264(L)HG-133B1.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 4:
Pin Assignment
(144-Pin SODIMM Front)
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
DQ14
DQ15
V
SS
NC
NC
CK0
V
DD
RAS#
WE#
S0#
S1#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
NC
Vss
NC
NC
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
109
A9
111
A10
113
V
DD
115 DQMB2
117 DQMB3
119
V
SS
121 DQ24
123 DQ25
125 DQ26
127 DQ27
129
V
DD
131 DQ28
133 DQ29
135 DQ30
137 DQ31
139
V
SS
141
SDA
143
V
DD
Table 5:
Pin Assignment
(144-Pin SODIMM Back)
38
DQ40
40
DQ41
42
DQ42
44
DQ43
46
V
DD
48
DQ44
50
DQ45
52
DQ46
54
DQ47
56
V
SS
58
NC
60
NC
62
CKE0
64
V
DD
66
CAS#
68
CKE1
70 NC/A12
1
72
NC
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
CK1
V
SS
NC
NC
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
110
BA1
112
A11
114
V
DD
116 DQMB6
118 DQMB7
120
V
SS
122 DQ56
124 DQ57
126 DQ58
128 DQ59
130
V
DD
132 DQ60
134 DQ61
136 DQ62
138 DQ63
140
V
SS
142
SCL
144
V
DD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Vss
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
DD
A3
A4
A5
V
SS
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQMB0
DQMB1
V
DD
A0
A1
A2
V
SS
1. Pin 70 is No Connect for 256MB modules, or A12 for 512MB modules.
Figure 2: Pin Locations (144-Pin SODIMM)
Front View
U1
U2
U17
Back View
U10
U9
U3
U4
U5
U6
U7
U8
U16
U15
U14
U13
U12
U11
PIN 1
(all odd pins)
PIN 143
PIN 144
(all even pins)
PIN 2
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 6:
Pin Descriptions
SYMBOL
RAS#, CAS#, WE#
CK0, CK1
DESCRIPTION
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all device banks idle),
ACTIVE power-down (row ACTIVE in any device bank), or
CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Input Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Input Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address inputs: Provide the row address for ACTIVE commands
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Input Serial clock for presence-detect: scl is used to synchronize the
presence-detect data transfer to and from the module.
Input/ Serial presence-detect data: sda is a bidirectional pin used to
Output transfer addresses and data into and data out of the presence-
detect portion of the module.
Input/ Data I/O: Data bus.
Output
TYPE
Input
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
65, 66, 67
61, 74
62, 68
CKE0, CKE1
69, 71
S0#,S1#
23, 24, 25, 26, 115, 116, 117,
118
DQMB0–DQMB7
106, 110
BA0, BA1
29, 30, 31, 32, 33, 34,
70
(512MB),
103, 104, 105,
109, 111, 112
A0–A11
(256MB)
A0–A12
(512MB)
142
141
SCL
SDA
3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,
16, 17, 18,19, 20, 37, 38, 39,
40, 41, 42, 43, 44, 47, 48, 49,
50, 51, 52, 53, 54, 83, 84, 85,
86, 87, 88, 89, 90, 93, 94, 95,
96, 97, 98, 99, 100, 121, 122,
123, 124, 125, 126, 127, 128,
131, 132, 133, 134, 135, 136,
137, 138
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
DQ0–DQ63
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 6:
Pin Descriptions (Continued)
SYMBOL
V
DD
TYPE
DESCRIPTION
Supply Power supply: +3.3V ±0.3V.
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS
11, 12, 27, 28, 45, 46, 63, 64,
81, 82, 101, 102, 113, 114, 129,
130, 143, 144
1, 21, 35, 55, 75, 91, 107, 119,
139, 2, 22, 36, 56, 76, 92, 108,
120, 140
57, 58, 59, 60, 70 (256MB), 72,
73, 77, 78, 79, 80
V
SS
Supply Ground.
NC
–
Not connected: These pins should be left unconnected.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
