2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM
Features
DDR3 SDRAM VLP RDIMM
MT18JBF25672P – 2GB
MT18JBZF25672P – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, very low profile registered dual in-line
memory module (VLP RDIMM)
• Compatible with ATCA form factors
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 2GB (256 Meg x 72)
• V
DD
= 1.5V ±0.075V
• V
DDSPD
= +3.0V to +3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data and strobe signals
• Single rank
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Pb-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin VLP RDIMM
(ATCA Compatible R/C M)
PCB height: 17.9mm (0.705in)
Options
Marking
• Full module heat spreader
Z
1
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
None
–
Industrial (–40°C
≤
T
A
≤
+85°C)
I
• Package
–
240-pin DIMM
Y
• Frequency/CAS latency
–
1.5ns @ CL = 8 (DDR3-1333)
2
-1G5
–
1.5ns @ CL = 9 (DDR3-1333)
-1G4
2
–
1.5ns @ CL = 10 (DDR3-1333)
-1G3
–
1.87ns @ CL = 7 (DDR3-1066)
-1G1
2
–
1.87ns @ CL = 8 (DDR3-1066)
-1G0
2
–
2.5ns @ CL = 5 (DDR3-800)
-80C
2
–
2.5ns @ CL = 6 (DDR3-800)
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-1G5
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
CL = 10
1333
1333
1333
–
–
–
–
CL = 9
1333
1333
–
–
–
–
–
CL = 8
1333
1066
1066
1066
1066
–
–
CL = 7
1066
1066
–
1066
–
–
–
CL = 6
800
800
800
800
800
800
800
CL = 5
800
–
–
–
–
800
–
t
RCD
(ns)
12
13.5
15
RP
(ns)
12
13.5
15
13.125
15
12.5
15
t
RC
(ns)
48
49.5
51
50.625
52.5
50
52.5
t
13.125
15
12.5
15
PDF: 09005aef83244ee6/Source: 09005aef83244f69
JBF18C256x72PY.fm - Rev. B 6/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
2GB
8K
16K (A[13:0])
8 (BA[2:0])
1Gb (256 Meg x 4)
2K (A[11, 9:0])
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M4,
1
1Gb DDR3 SDRAM
Part Number
2
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
2GB
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
Module
Bandwidth
10.6 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
8-8-8
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
MT18JBF25672P(I)Y-1G5__
MT18JBF25672P(I)Y-1G4__
MT18JBF25672P(I)Y-1G3__
MT18JBF25672P(I)Y-1G1__
MT18JBF25672P(I)Y-1G0__
MT18JBF25672P(I)Y-80C__
MT18JBF25672P(I)Y-80B__
Table 4:
Part Numbers and Timing Parameters – 2GB Modules With Heat Spreader
Base device: MT41J256M4,
1
1Gb DDR3 SDRAM
Part Number
2
MT18JBZF25672P(I)Y-1G5__
MT18JBZF25672P(I)Y-1G4__
MT18JBZF25672P(I)Y-1G3__
MT18JBZF25672P(I)Y-1G1__
MT18JBZF25672P(I)Y-1G0__
MT18JBZF25672P(I)Y-80C__
MT18JBZF25672P(I)Y-80B__
Notes:
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
2GB
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
Module
Bandwidth
10.6 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
8-8-8
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT18JBF25672PY-1G1D1.
PDF: 09005aef83244ee6/Source: 09005aef83244f69
JBF18C256x72PY.fm - Rev. B 6/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
240-Pin DDR3 VLP RDIMM Front
240-Pin DDR3 VLP RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
DQ
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
54
55
56
57
58
59
60
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
TT
V
TT
CKE0
V
DD
BA2
V
DD
A11
A7
V
DD
A5
A4
V
DD
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
84
85
86
87
88
89
90
A2
V
DD
NC
NC
V
DD
V
DD
V
REF
CA
P
AR
_I
N
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
NC
NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
121
122
123
124
125
126
127
128
129
130
131
132
133
134
136
137
138
139
140
141
142
143
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DQS9
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DQS10
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DQS11
V
SS
DQ22
DQ23#
V
SS
DQ28
DQ29
151
152
154
155
156
157
158
159
160
161
163
164
166
167
168
169
170
171
172
173
175
176
177
178
179
180
V
SS
DQS12
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DQS17
V
SS
CB6
CB7
V
SS
NC
RESET#
NC
V
DD
A15
A14
V
DD
A12
A9
V
DD
A8
A6
V
DD
A3
181
182
184
185
186
188
189
190
191
193
194
195
196
197
198
199
200
201
202
203
205
206
207
208
209
210
A1
V
DD
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DD
RAS#
S0#
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DQS13
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
211
212
214
215
216
218
219
220
221
223
224
225
226
227
228
229
230
232
233
235
236
237
238
239
240
V
SS
DQS14
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DQS15
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS16
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
153 DQS12# 183
213 DQS14#
187 EVENT# 217
162 DQS17# 192
222 DQS15#
135 DQS10# 165
231 DQS16#
53 E
RR
_O
UT
# 83
144 DQS11# 174
204 DQS13# 234
PDF: 09005aef83244ee6/Source: 09005aef83244f69
JBF18C256x72PY.fm - Rev. B 6/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[15:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
.
A[13:0] address the 1Gb DDR3 devices. A[15:14] are needed to
calculate parity on the command/address bus.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0] are used
as part of the parity calculation.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
and
DC LOW
≤
0.2 × V
DD
. RESET# assertion and deassertion are asynchronous. System
applications will most likely be unterminated, heavily loaded, and have very slow slew
rates. A slow slew rate receiver design is recommended along with implementing on-chip
noise filtering to prevent false triggering (RESET# assertion minimum pulse width is
100ns).
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize
communication to and from the temperature sensor/SPD EEPROM.
Check bits:
Data used for ECC.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
BA[2:0]
Input
CK0, CK0#
Input
CKE0
ODT0
Input
Input
P
AR
_I
N
RAS#, CAS#,
WE#
RESET#
Input
Input
Input
(LVCMOS)
S0#
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[17:0],
DQS#[17:0]
SDA
E
RR
_O
UT
#
EVENT#
Input
Input
Input
I/O
I/O
I/O
I/O
Output
Parity error output:
Parity error found on the command and address bus.
(open drain)
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
PDF: 09005aef83244ee6/Source: 09005aef83244f69
JBF18C256x72PY.fm - Rev. B 6/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
V
DD
V
DDSPD
V
REF
CA
V
REF
DQ
V
SS
V
TT
NC
NF
Pin Descriptions (continued)
Type
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Description
Power supply:
1.5V ±0.075V. The component V
DD
and V
DD
Q are connected to the
module V
DD
.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
Control, command, and address (V
DD
/2).
Reference voltage:
DQ, DM (V
DD
/2).
Ground.
Termination voltage:
Used for control, command, and address (V
DD
/2).
No connect:
These pins are not connected on the module.
No function:
Connected within the module, but provides no functionality.
PDF: 09005aef83244ee6/Source: 09005aef83244f69
JBF18C256x72PY.fm - Rev. B 6/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
FPGA/CPLD
