128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Q-FLASH
TM
MEMORY
FEATURES
• x8/x16 organization
• One hundred twenty-eight 128KB erase blocks
(128Mb)
Sixty-four 128KB erase blocks (64Mb)
Thirty-two 128KB erase blocks (32Mb)
• V
CC
, V
CC
Q, and V
PEN
voltages:
2.7V to 3.6V V
CC
operation
2.7V to 3.6V or 4.5V to 5.5V* V
CC
Q operation
2.7V to 3.6V, or 5V V
PEN
application programming
• Interface Asynchronous Page Mode Reads:
150ns/25ns read access time (128Mb)
120ns/25ns read access time (64Mb)
110ns/25ns read access time (32Mb)
• Enhanced data protection feature with V
PEN
= V
SS
Flexible sector locking
Sector erase/program lockout during power
transition
• Security OTP block feature
Permanent block locking (Contact factory for
availability)
• Industry-standard pinout
• Inputs and outputs are fully TTL-compatible
• Common Flash Interface (CFI) and Scalable
Command Set
• Automatic write and erase algorithm
• 4.7µs-per-byte effective programming time using
write buffer
• 128-bit protection register
64-bit unique device identifier
64-bit user-programmable OTP cells
• 100,000 ERASE cycles per block
• Automatic suspend options:
Block Erase Suspend-to-Read
Block Erase Suspend-to-Program
Program Suspend-to-Read
NOTE:
MT28F128J3, and MT28F320J3 are preliminary status.
‡
MT28F640J3 is production status.
MT28F128J3
‡
, MT28F640J3,
MT28F320J3
‡
56-Pin TSOP Type I
64-Ball FBGA
OPTIONS
• Timing
150ns (128Mb)
120ns (64Mb)
110ns (32Mb)
• Operating Temperature Range
Commercial Temperature (0ºC to +85ºC)
Extended Temperature (-40ºC to +85ºC)
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
MARKING
-15
-12
-11
None
ET
• V
CC
Q Option*
2.7V–3.6V
4.5V–5.5V
• Packages
56-pin TSOP Type I
64-ball FBGA (1.0mm pitch)
Part Number Example:
None
F
RG
FS
MT28F640J3RG-12 ET
*Contact factory for availability of the MT28F320J3 and
MT28F640J3.
1
©2002, Micron Technology, Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
GENERAL DESCRIPTION
The MT28F128J3 is a nonvolatile, electrically block-
erasable (Flash), programmable memory containing
134,217,728 bits organized as 16,777,218 bytes (8 bits)
or 8,388,608 words (16 bits). This 128Mb device is orga-
nized as one hundred twenty-eight 128KB erase blocks.
The MT28F640J3 contains 67,108,864 bits organized
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
This 64Mb device is organized as sixty-four 128KB erase
blocks.
Similarly, the MT28F320J3 contains 33,554,432 bits
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
(16 bits). This 32Mb device is organized as thirty-two
128KB erase blocks.
These three devices feature in-system block lock-
ing. They also have common flash interface (CFI) that
permits software algorithms to be used for entire fami-
lies of devices. The software is device-independent,
JEDEC ID-independent with forward and backward
compatibility.
Additionally, the scalable command set (SCS) al-
lows a single, simple software driver in all host systems
to work with all SCS-compliant Flash memory devices.
The SCS provides the fastest system/device data trans-
fer rates and minimizes the device and system-level
implementation costs.
To optimize the processor-memory interface, the
device accommodates V
PEN
, which is switchable during
block erase, program, or lock bit configuration, or
hardwired to V
CC
, depending on the application. V
PEN
is
treated as an input pin to enable erasing, program-
ming, and block locking. When V
PEN
is lower than the
V
CC
lockout voltage (V
LKO
), all program functions are
disabled. Block erase suspend mode enables the user
to stop block erase to read data from or program data to
any other blocks. Similarly, program suspend mode
enables the user to suspend programming to read data
or execute code from any unsuspended blocks.
V
PEN
serves as an input with 2.7V, 3.3V, or 5V for
application programming. V
PEN
in this Q-Flash family
can provide data protection when connected to ground.
This pin also enables program or erase lockout during
power transition.
Micron’s even-sectored Q-Flash devices offer indi-
vidual block locking that can lock and unlock a block
using the sector lock bits command sequence.
Status (STS) is a logic signal output that gives an
additional indicator of the internal state machine (ISM)
activity by providing a hardware signal of both status
and status masking. This status indicator minimizes
central processing unit (CPU) overhead and system
power consumption. In the default mode, STS acts as
an RY/BY# pin. When LOW, STS indicates that the ISM
is performing a block erase, program, or lock bit con-
figuration. When HIGH, STS indicates that the ISM is
ready for a new command.
Three chip enable (CE) pins are used for enabling and
disabling the device by activating the device’s control
logic, input buffer, decoders, and sense amplifiers.
BYTE# enables selecting x8 or x16 READs/WRITEs
to the device. BYTE# at logic LOW selects an 8-bit mode
with address A0 selecting between the low byte
and the high byte. BYTE# at logic HIGH enables 16-bit
operation.
RP# is used to reset the device. When the device is
disabled and RP# is at V
CC
, the standby mode is en-
abled. A reset time (
t
RWH) is required after RP#
switches HIGH until outputs are valid. Likewise, the
device has a wake time (
t
RS) from RP# HIGH until
WRITEs to the command user interface (CUI) are rec-
ognized. When RP# is at GND, it provides write protec-
tion, resets the ISM, and clears the status register.
A variant of the MT28F320J3 also supports the new
security block lock feature for additional code security.
This feature provides an OTP function for locking the
top two blocks, the bottom two blocks, or the entire
device. (Contact factory for availability.)
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F320J3FS-11
MT28F320J3FS-11 ET
MT28F640J3FS-12
MT28F640J3FS-12 ET
MT28F128J3FS-15
MT28F128J3FS-15 ET
PRODUCT
MARKING
FW201
FW207
FW202
FW209
FW203
FW501
ENGINEERING
SAMPLE
FX201
FX207
FX202
FX209
FX203
FX501
QUALIFIED
SAMPLE
FQ201
FQ207
FQ202
FQ209
FQ203
FQ501
PIN /BALL ASSIGNMENT (Top View)
56-Pin TSOP Type I
A22
CE1
A21
A20
A19
A18
A17
A16
V
CC
A15
A14
A13
A12
CE0
V
PEN
RP#
A11
A10
A9
A8
V
SS
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
V
SS
DQ13
DQ5
DQ12
DQ4
V
CC
Q
V
SS
DQ11
DQ3
DQ10
DQ2
V
CC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
A23
CE2
64-Ball FBGA
1
A
B
C
D
E
F
G
H
A1
2
A6
3
A8
4
V
PEN
5
A13
6
V
CC
7
A18
8
A22
A2
V
SS
A9
CE0
A14
DNU
A19
CE1
A3
A7
A10
A12
A15
DNU
A20
A21
A4
A5
A11
RP#
DNU
DNU
A16
A17
DQ8
DQ1
DQ9
DQ3
DQ4
DNU
DQ15
STS
BYTE#
DQ0
DQ10
DQ11
DQ12
DNU
DNU
OE#
A23
A0
DQ2
V
CC
Q
DQ5
DQ6
DQ14
WE#
CE2
DNU
V
CC
V
SS
DQ13
V
SS
DQ7
NC
Top View
(Ball Down)
NOTE:
1. A22 only exists on the 64Mb and 128Mb devices. On the 32Mb, this pin/ball is a no connect (NC).
2. A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball is a no connect (NC).
3. The # symbol indicates signal is active LOW.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
(128Mb)
Input
Buffer
I/O
Control
Logic
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
Addr.
A0–A23
Buffer/
Latch
X - Decoder/Block Erase Control
Power
(Current)
Control
Addr.
Counter
Write
Buffer
DQ0–DQ15
128KB Memory Block (125)
128KB Memory Block (126)
128KB Memory Block (127)
CE0
CE1
CE2
OE#
WE#
RP#
V
CC
STS
V
PEN
CE Logic
Command
Execution
Logic
State
Machine
Y-
Decoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
V
PP
Switch/
Pump
Status
Register
Identification
Register
Query
Output
Buffer
FUNCTIONAL BLOCK DIAGRAM
(64Mb)
Input
Buffer
I/O
Control
Logic
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
Addr.
A0–A22
Buffer/
Latch
X - Decoder/Block Erase Control
Power
(Current)
Control
Addr.
Counter
Write
Buffer
DQ0–DQ15
128KB Memory Block (61)
128KB Memory Block (62)
128KB Memory Block (63)
CE0
CE1
CE2
OE#
WE#
RP#
V
CC
STS
V
PEN
CE Logic
Command
Execution
Logic
State
Machine
Y-
Decoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
V
PP
Switch/
Pump
Status
Register
Identification
Register
Query
Output
Buffer
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
(32Mb)
Input
Buffer
I/O
Control
Logic
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
Addr.
A0–A21
Buffer/
Latch
X - Decoder/Block Erase Control
Power
(Current)
Control
Addr.
Counter
Write
Buffer
DQ0–DQ15
128KB Memory Block (29)
128KB Memory Block (30)
128KB Memory Block (31)
CE0
CE1
CE2
OE#
WE#
RP#
V
CC
STS
V
PEN
CE Logic
Command
Execution
Logic
State
Machine
Y-
Decoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
V
PP
Switch/
Pump
Status
Register
Identification
Register
Query
Output
Buffer
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
