4Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
Features
•
•
•
•
•
V
DD
= V
DDQ
= 1.2V ±60mV
V
PP
= 2.5V, –125mV/+250mV
On-die, internal, adjustable V
REFDQ
generation
1.2V pseudo open-drain I/O
T
C
maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
sPPR and hPPR capability
JEDEC JESD-79-4 compliant
Options
1
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 11.5mm) – Rev. A
– 78-ball (9mm x 10.5mm) – Rev. B
– 78-ball (8mm x 12mm) – Rev. E
– 78-ball (7.5mm x 11mm) – Rev. F
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. A
– 96-ball (9mm x 14mm) – Rev. B
– 96-ball (7.5mm x 13.5mm) – Rev. E, F
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.682ns @ CL = 20 (DDR4-2933)
– 0.682ns @ CL = 21 (DDR4-2933)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.750ns @ CL = 19 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
– 1.071ns @ CL = 13 (DDR4-1866)
• Operating temperature
– Commercial (0° T
C
95°C)
– Industrial (–40° T
C
95°C)
– Revision
Marking
1G4
512M8
256M16
2
HX
RH
WE
SA
HA
GE
LY
-062E
-068E
-068
-075E
-075
-083E
-083
-093E
-093
-107E
None
IT
:A
:B
:E
:F
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Notes:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
2. Not available on Rev. A.
3. Restricted and limited availability.
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
1
-062Y
-062E
-068
-075E
-075
-083E
-083
-093E
-093
-107E
Note:
Data Rate (MT/s)
3200
3200
2933
2666
2666
2400
2400
2133
2133
1866
Target
t
RCD-
t
RP-CL
22-22-22
22-22-22
21-21-21
18-18-18
19-19-19
16-16-16
17-17-17
15-15-15
16-16-16
13-13-13
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.75 (13.32)
13.75
14.32 (13.75)
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
13.92 (13.50)
13.75 (13.32)
13.75
14.32 (13.75)
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
13.92 (13.50)
13.75 (13.32)
13.75
14.32 (13.75)
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
13.92 (13.50)
1. Refer to the Speed Bin Tables for additional details.
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page size
1
Notes:
1024 Meg x 4
4
BG[1:0]
4
BA[1:0]
64K (A[15:0])
1K (A[9:0])
512B / 1KB
2
512 Meg x 8
4
BG[1:0]
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
1KB
256 Meg x 16
2
BG0
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
2KB
1. Page size is per bank, calculated as follows:
Page size = 2
COLBITS
× ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
2. Die revision dependant.
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 1: Order Part Number Example
Example Part Number: MT40A1G4-083:B
-
MT40A
Configuration
Package
Speed
:
Revision
{
Configuration
1 Gig x 4
512 Meg x 8
256Meg x 16
1G4
512M8
256M16
Mark
HX
RH
WE
SA
HA
GE
LY
–107E
–093
–093E
–083
–083E
–075
–075E
–068
–068E
–062E
Revision
:A, :B, :E, :F
Case Temperature
Commercial
Package
78-ball 9.0mm x 11.5mm FBGA
78-ball 9.0mm x 10.5mm FBGA
78-ball 8.0mm x 12.0mm FBGA
78-ball 7.5mm x 11.0mm FBGA
96-ball 9.0mm x 14.0mm FBGA
96-ball 9.0mm x 14.0mm FBGA
96-ball 7.5mm x 13.5mm FBGA
Industrial
Speed Grade
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
None
IT
= 1.071ns, CL = 13
= 0.937ns, CL = 16
= 0.937ns, CL = 15
= 0.833ns, CL = 17
= 0.833ns, CL = 16
= 0.750ns, CL = 19
= 0.750ns, CL = 18
= 0.682ns, CL = 21
= 0.682ns, CL = 20
= 0.625ns, CL = 22
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
Contents
Important Notes and Warnings .......................................................................................................................
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Functional Block Diagrams .............................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT R
TT(NOM)
Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
DQ RX EQ ..................................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Hard Post Package Repair Mode ..................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
WRITE Preamble ........................................................................................................................................
READ Preamble ..........................................................................................................................................
19
19
19
20
20
21
21
22
24
26
29
36
38
39
39
42
43
44
47
49
50
50
50
50
51
52
53
53
53
53
54
54
54
55
57
57
57
57
58
59
60
60
60
60
60
61
62
62
63
63
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR4 SDRAM
Features
READ Preamble Training ............................................................................................................................ 63
Temperature-Controlled Refresh ................................................................................................................. 63
Command Address Latency ........................................................................................................................ 63
Internal V
REF
Monitor ................................................................................................................................. 63
Maximum Power Savings Mode ................................................................................................................... 64
Mode Register 5 .............................................................................................................................................. 65
Data Bus Inversion ..................................................................................................................................... 66
Data Mask .................................................................................................................................................. 67
CA Parity Persistent Error Mode .................................................................................................................. 67
ODT Input Buffer for Power-Down .............................................................................................................. 67
CA Parity Error Status ................................................................................................................................. 67
CRC Error Status ......................................................................................................................................... 67
CA Parity Latency Mode .............................................................................................................................. 67
Mode Register 6 .............................................................................................................................................. 68
t
CCD_L Programming ................................................................................................................................. 69
V
REFDQ
Calibration Enable .......................................................................................................................... 69
V
REFDQ
Calibration Range ........................................................................................................................... 69
V
REFDQ
Calibration Value ............................................................................................................................ 70
DQ RX EQ .................................................................................................................................................. 70
Truth Tables ................................................................................................................................................... 71
NOP Command .............................................................................................................................................. 74
DESELECT Command .................................................................................................................................... 74
DLL-Off Mode ................................................................................................................................................ 74
DLL-On/Off Switching Procedures .................................................................................................................. 76
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 76
DLL-Off to DLL-On Procedure .................................................................................................................... 78
Input Clock Frequency Change ....................................................................................................................... 79
Write Leveling ................................................................................................................................................ 80
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 81
Procedure Description ................................................................................................................................ 82
Write Leveling Mode Exit ............................................................................................................................ 83
Command Address Latency ............................................................................................................................ 85
Low-Power Auto Self Refresh Mode ................................................................................................................. 90
Manual Self Refresh Mode .......................................................................................................................... 90
Multipurpose Register .................................................................................................................................... 92
MPR Reads ................................................................................................................................................. 93
MPR Readout Format ................................................................................................................................. 95
MPR Readout Serial Format ........................................................................................................................ 95
MPR Readout Parallel Format ..................................................................................................................... 96
MPR Readout Staggered Format .................................................................................................................. 97
MPR READ Waveforms ............................................................................................................................... 98
MPR Writes ............................................................................................................................................... 100
MPR WRITE Waveforms ............................................................................................................................. 101
MPR REFRESH Waveforms ........................................................................................................................ 102
Gear-Down Mode .......................................................................................................................................... 105
Maximum Power-Saving Mode ....................................................................................................................... 108
Maximum Power-Saving Mode Entry .......................................................................................................... 108
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 109
CKE Transition During Maximum Power-Saving Mode ................................................................................ 109
Maximum Power-Saving Mode Exit ............................................................................................................ 109
Command/Address Parity .............................................................................................................................. 111
Per-DRAM Addressability .............................................................................................................................. 119
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
