ADVANCE
‡
2 MEG x 16, 1 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
ASYNCHRONOUS
CellularRAM
TM
Features
• Asynchronous and Page Mode interface
• Random Access Time: 70ns, 85ns
• Page Mode Read Access
Sixteen-word page size
Interpage read access: 70ns, 85ns
Intrapage read access: 20ns, 25ns
• V
CC
, V
CC
Q Voltages
1.70V–1.95V V
CC
1.70V–2.25V V
CC
Q (Option W)
2.30V–2.70V V
CC
Q (Option V—contact factory)
2.70V–3.30V V
CC
Q (Option L)
• Low Power Consumption
Asynchronous READ < 25mA
Intrapage READ < 15mA
Standby: 110µA (32Mb—standard), 70µA (16Mb)
90µA (32Mb—low-power option)
Deep Power-Down < 10µA
• Low-Power Features
Temperature Compensated Refresh (TCR)
On-Chip Sensor Control
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
MT45W2MW16PAFA
MT45W2ML16PAFA
MT45W1MW16PAFA
MT45W1ML16PAFA
Figure 1: 48-Ball FBGA
1
A
B
C
D
E
F
G
H
LB#
2
OE#
3
A0
4
A1
5
A2
6
ZZ#
DQ8
UB#
A3
A4
CE#
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
V
SS
Q
DQ11
A17
A7
DQ3
V
CC
V
CC
Q
DQ12
NC
A16
DQ4
V
SS
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
A19
A12
A13
WE#
DQ7
A18
A8
A9
A10
A11
A20
Top View
(Bump Down)
NOTE:
Options
Designator
• Configuration
2 Meg x 16
1 Meg x 16
• Vcc Core Voltage Supply
1.8V – MT45WxMx16PA
• VccQ I/O Voltage
3.0V – MT45WxML16PA
2.5V – MT45WxMV16PA
1.8V – MT45WxMW16PA
• Package
48-ball FBGA
48-ball FBGA—Lead-free
• Access Time
60ns
70ns
85ns
See Table 1 on page 3 for Ball Descriptions. See Figure 21
on page 24 for the 48-ball mechanical drawing.
Options (continued)
Designator
MT45W2Mx16PA
MT45W1Mx16PA
W
L
V
1
W
FA
BA
1
-60
1
-70
-85
• Standby Power
Standard
Low-Power (32Mb)
• Operating Temperature Range
Wireless (-25°C to +85°C)
Industrial (-40°C to +85°C)
None
L
WT
IT
1
Note 1: Contact factory.
Part Number Example:
MT45W2ML16PAFA-70LWT
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
1
©2004 Micron Technology, Inc. All Rights Reserved.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
2 MEG x 16, 1 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
General Description
Micron
CellularRAM products are high-speed,
CMOS dynamic random access memories that have
been developed for low-power portable applications.
The MT45W2Mx16PA is a 32Mb device organized as 2
Meg x 16 bits, and the MT45W1Mx16PA is a 16Mb
device organized as 1 Meg x 16 bits. These devices
include the industry-standard, asynchronous memory
interface found on other low-power SRAM or Pseudo
SRAM offerings.
Operating voltages have been reduced in an effort to
minimize power consumption. The core voltage has
been reduced to a 1.80V operating level. To maintain
compatibility with different memory bus interfaces,
CellularRAM devices are available with I/O voltages of
3.00V, 2.50V or 1.80V.
A user-accessible configuration register (CR) defines
how the CellularRAM device performs on-chip refresh
and whether page mode read accesses are permitted.
This register is automatically loaded with a default set-
ting during power-up and can be updated at any time
during normal operation.
To operate seamlessly on an asynchronous memory
bus, CellularRAM products incorporate a transparent
self refresh mechanism. The hidden refresh requires
no additional support from the system memory con-
troller and has no significant impact on device read/
write performance.
Special attention has been focused on current con-
sumption during self refresh. CellularRAM products
include three system-accessible mechanisms to mini-
mize refresh current. Temperature compensated
refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The
refresh rate decreases at lower temperatures to mini-
mize current consumption during standby. TCR can
also be set by the system for maximum device temper-
atures of +85°C, +45°C, and +15°C. Setting the sleep
enable pin ZZ# to LOW enables one of two low-power
modes: partial array refresh (PAR); or deep power-
down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts
refresh operation altogether and is used when no vital
information is stored in the device. These three refresh
mechanisms are accessed through the CR.
Figure 2: Functional Block Diagram
2 Meg x 16 and 1 Meg x 16
A[20:0]
(for 32Mb)
A[19:0]
(for 16Mb)
Address Decode
Logic
2,048K x 16
(1,024K x 16)
DRAM
MEMORY
ARRAY
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Configuration
Register (CR)
CE#
WE#
OE#
UB#
LB#
ZZ#
Control
Logic
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All Rights Reserved.
ADVANCE
2 MEG x 16, 1 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Table 1:
FBGA BALL
ASSIGNMENT
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3, H1, G2,
H6
A6
B5
A2
G5
A1
B2
B6, C5, C6, D5,
E5, F5, F6, G6,
B1, C1, C2, D2,
E2, F2, F1, G1
E3
D6
E1
E6
D1
FBGA Ball Descriptions
SYMBOL
A[20:0]
TYPE
Input
DESCRIPTION
Address Inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the CR. On
the 16Mb device, A20 (ball H6) is not internally connected.
ZZ#
CE#
OE#
WE#
LB#
UB#
DQ[15:0]
Input
Input
Input
Input
Input
Input
Input/
Output
Sleep Enable: When ZZ# is LOW, the CR can be loaded or the device can enter one
of two low-power modes (DPD or PAR).
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Enables WRITE operations when LOW.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
NC
V
CC
V
CC
Q
V
SS
V
SS
Q
—
Supply
Supply
Supply
Supply
Not internally connected.
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.8V, 2.5V, 3.0V) Power supply for input/output buffers.
V
SS
must be connected to ground.
V
SS
Q must be connected to ground.
Table 2:
MODE
Standby
Read
Write
No Operation
PAR
DPD
Load
Configuration
Register
NOTE:
Bus Operations
POWER
Standby
Active
Active
Idle
Partial Array Refresh
Deep Power-Down
Active
CE#
H
L
L
L
H
H
L
WE#
X
H
L
X
X
X
L
OE#
X
L
X
X
X
X
X
LB#/UB#
X
L
L
X
X
X
X
ZZ#
H
H
H
H
L
L
L
DQ[15:0]
1
High-Z
Data-Out
Data-In
X
High-Z
High-Z
High-Z
NOTES
2, 5
1, 4
1, 3, 4
4, 5
6
6
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0]
are affected. When UB# only is in the select mode, DQ[15:8] are affected.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are inter-
nally isolated from any external influence.
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. V
IN
= V
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All Rights Reserved.
ADVANCE
2 MEG x 16, 1 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Table 3:
Abbreviated Component Marks—
CellularRAM FBGA-Packaged Components
ENGINEERING
SAMPLE
PX400
PX401
PX403
PX404
PX104
PX105
PX107
PX108
QUALIFIED
PRODUCT
PW400
PW401
PW403
PW404
PW104
PW105
PW107
PW108
PART NUMBER
MT45W2MW16PAFA-85 WT
MT45W2MW16PAFA-70 WT
MT45W2ML16PAFA-85 WT
MT45W2ML16PAFA-70 WT
MT45W1MW16PAFA-85 WT
MT45W1MW16PAFA-70 WT
MT45W1ML16PAFA-85 WT
MT45W1ML16PAFA-70 WT
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All Rights Reserved.
ADVANCE
2 MEG x 16, 1 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Functional Description
In general, the MT45W2Mx16PA device and the
MT45W1Mx16PA device are high-density alternatives to
SRAM and Pseudo SRAM products, popular in low-
power, portable applications. The MT45W2Mx16PA
contains 33,554,432 bits organized as 2,097,152
addresses by 16 bits.The MT45W1Mx16PA contains
16,777,216 bits organized as 1,048,576 addresses by 16
bits. These devices include the industry-standard, asyn-
chronous memory interface found on other low-power
SRAM or Pseudo SRAM offerings. Page mode accesses
are also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
Asynchronous Mode
CellularRAM products power up in the asynchro-
nous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, LB#/
UB#). READ operations (Figure 4) are initiated by
bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os
after the specified access time has elapsed. WRITE
operations (Figure 5) occur when CE#, WE#, and LB#/
UB# are driven LOW. During WRITE operations, the
level of OE# is a “Don't Care”; WE# will override OE#.
The data to be written will be latched on the rising edge
of CE#, WE#, or LB#/UB# (whichever occurs first).
Power-Up Initialization
CellularRAM products include an on-chip voltage
sensor that is used to launch the power-up initializa-
tion process. Initialization will load the CR with its
default setting. V
CC
and V
CC
Q must be applied simul-
taneously, and when they reach a stable level above
1.70V, the device will require 150µs to complete its self-
initialization process (see Figure 3 below). During the
initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for nor-
mal operation.
CE#
Figure 4: READ Operation
OE#
WE#
ADDRESS
ADDRESS VALID
DATA
DATA VALID
Figure 3: Power-Up Initialization
Timing
Vcc = 1.7V
Vcc
VccQ
t
PU >
150µs
LB#/UB#
Device Initialization
Device ready for
normal operation
t
RC = READ Cycle Time
DON’T CARE
Figure 5: WRITE Operation
Bus Operating Modes
The MT45W2Mx16PA and the MT45W1Mx16PA
CellularRAM products incorporate the industry-stan-
dard, asynchronous interface found on other low-
power SRAM or Pseudo SRAM offerings. This bus
interface supports asynchronous READ and WRITE
operations as well as the bandwidth-enhancing page
mode READ operation. The specific interface that is
supported is defined by the value loaded into the CR.
CE#
OE#
WE#
ADDRESS
DATA
LB#/UB#
ADDRESS VALID
DATA VALID
t
WC = WRITE Cycle Time
DON’T CARE
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All Rights Reserved.
