2Gb: x16, x32 Automotive LPDDR SDRAM
Features
Automotive LPDDR SDRAM
MT46H128M16LF – 32 Meg x 16 x 4 Banks
MT46H64M32LF – 16 Meg x 32 x 4 Banks
Features
• V
DD
/V
DDQ
= 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
2
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh; 32ms for the automotive temperature
range
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-48
Clock Rate
208 MHz
Access Time
4.8ns
Options
• V
DD
/V
DDQ
– 1.8V/1.8V
• Configuration
– 128 Meg x 16 (32 Meg x 16 x 4 banks)
– 64 Meg x 32 (16 Meg x 32 x 4 banks)
• Addressing
– JEDEC-standard
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm)
– 90-ball VFBGA (8mm x 13mm)
• Timing – cycle time
– 4.8ns @ CL = 3 (208 MHz)
• Special Options
– Automotive (package-level burn-in)
• Operating temperature range
– From –40˚C to +85˚C
– From –40˚C to +105˚C
1
• Design revision
Notes:
1. Contact factory for availability.
2. Self refresh supported up to 85 ºC.
Mark
H
128M16
64M32
LF
DD
BQ
-48
A
IT
AT
:C
Table 2: Configuration Addressing – 2Gb
Architecture
Configuration
Refresh count
Row addressing
Column addressing
128 Meg x 16
32 Meg x 16 x 4 banks
8K
16K A[13:0]
2K A11, A[9:0]
64 Meg x 32
16 Meg x 32 x 4 banks
8K
16K A[13:0]
1K A[9:0]
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t89m_auto_lpddr.pdf - Rev. I 05/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
See Package Block Diagrams for descriptions of signal connections and die configurations for each respective ar-
chitecture.
Figure 1: 2Gb Mobile LPDDR Part Numbering
MT 46
Micron Technology
Product Family
46 = Mobile LPDDR
H
64M32 LF KQ -6
A
IT
:C
Design Revision
:C = Design generation
Operating Temperature
IT = Industrial (–40°C to +85°C)
AT = Automotive (–40°C to +105°C)
WT = Wireless (–25°C to +85°C)
Operating Voltage
H = 1.8/1.8V
HC = 1.8/1.2V
Special Options
Configuration (depth, width)
128 Meg x 16
64 Meg x 32
128 Meg x 32
256 Meg x 32
Blank = None
A = Automotive
(Multiple processing codes are separated
by a space and are listed in hierarchical order.)
Speed Grade
-48 = 4.8ns
t
CK
-5 = 5ns
t
CK
Addressing
LF = JEDEC-standard addressing
L2 = 2-die stack standard addressing
L4 = 4-die stack standard addressing
Package Codes
DD = 60-ball (8mm x 9mm) VFBGA, “green”
BQ = 90-ball (8mm x 13mm) VFBGA, “green”
KQ = 168-ball (12mm x 12mm) WFBGA, “green”
LE = 168-ball (12mm x 12mm) TFBGA, “green”
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
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t89m_auto_lpddr.pdf - Rev. I 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
Contents
Important Notes and Warnings ......................................................................................................................... 8
General Description ......................................................................................................................................... 8
Functional Block Diagrams ............................................................................................................................. 10
Ball Assignments ............................................................................................................................................ 12
Ball Descriptions ............................................................................................................................................ 14
Package Block Diagrams ................................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 17
Electrical Specifications .................................................................................................................................. 19
Electrical Specifications – I
DD
Parameters ........................................................................................................ 22
Electrical Specifications – AC Operating Conditions ......................................................................................... 28
Output Drive Characteristics ........................................................................................................................... 32
Functional Description ................................................................................................................................... 35
Commands .................................................................................................................................................... 36
DESELECT ................................................................................................................................................. 37
NO OPERATION ......................................................................................................................................... 37
LOAD MODE REGISTER ............................................................................................................................. 37
ACTIVE ...................................................................................................................................................... 37
READ ......................................................................................................................................................... 38
WRITE ....................................................................................................................................................... 39
PRECHARGE .............................................................................................................................................. 40
BURST TERMINATE ................................................................................................................................... 41
AUTO REFRESH ......................................................................................................................................... 41
SELF REFRESH ........................................................................................................................................... 42
DEEP POWER-DOWN ................................................................................................................................. 42
Truth Tables ................................................................................................................................................... 43
State Diagram ................................................................................................................................................ 48
Initialization .................................................................................................................................................. 49
Standard Mode Register .................................................................................................................................. 52
Burst Length .............................................................................................................................................. 53
Burst Type .................................................................................................................................................. 53
CAS Latency ............................................................................................................................................... 54
Operating Mode ......................................................................................................................................... 55
Extended Mode Register ................................................................................................................................. 56
Temperature-Compensated Self Refresh ...................................................................................................... 56
Partial-Array Self Refresh ............................................................................................................................ 57
Output Drive Strength ................................................................................................................................ 57
Status Read Register ....................................................................................................................................... 58
Bank/Row Activation ...................................................................................................................................... 60
READ Operation ............................................................................................................................................. 61
WRITE Operation ........................................................................................................................................... 72
PRECHARGE Operation .................................................................................................................................. 84
Auto Precharge ............................................................................................................................................... 84
Concurrent Auto Precharge ......................................................................................................................... 84
AUTO REFRESH Operation ............................................................................................................................. 90
SELF REFRESH Operation ............................................................................................................................... 91
Power-Down .................................................................................................................................................. 93
Deep Power-Down ..................................................................................................................................... 94
Clock Change Frequency ................................................................................................................................ 96
Revision History ............................................................................................................................................. 97
Rev. I – 05/18 .............................................................................................................................................. 97
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t89m_auto_lpddr.pdf - Rev. I 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
Rev. H - 01/17 .............................................................................................................................................
Rev. G - 02/15 .............................................................................................................................................
Rev. F - 09/14 ..............................................................................................................................................
Rev. E – 07/14 .............................................................................................................................................
Rev. D – 03/14 .............................................................................................................................................
Rev. C – 02/14 .............................................................................................................................................
Rev. B – 01/14 .............................................................................................................................................
Rev. B – 11/13 .............................................................................................................................................
Rev. A – 07/13 .............................................................................................................................................
97
97
97
97
97
97
97
97
97
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t89m_auto_lpddr.pdf - Rev. I 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Automotive LPDDR SDRAM
Features
List of Figures
Figure 1: 2Gb Mobile LPDDR Part Numbering .................................................................................................. 2
Figure 2: Functional Block Diagram (x16) ....................................................................................................... 10
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 11
Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 12
Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 13
Figure 6: Single Rank, Single Channel (1 Die) Package Block Diagram .............................................................. 16
Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: DD ............................................................................. 17
Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: BQ ............................................................................ 18
Figure 9: Typical Self Refresh Current vs. Temperature .................................................................................... 27
Figure 10: ACTIVE Command ........................................................................................................................ 38
Figure 11: READ Command ........................................................................................................................... 39
Figure 12: WRITE Command ......................................................................................................................... 40
Figure 13: PRECHARGE Command ................................................................................................................ 41
Figure 14: DEEP POWER-DOWN Command ................................................................................................... 42
Figure 15: Simplified State Diagram ............................................................................................................... 48
Figure 16: Initialize and Load Mode Registers ................................................................................................. 50
Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 51
Figure 18: Standard Mode Register Definition ................................................................................................. 52
Figure 19: CAS Latency .................................................................................................................................. 55
Figure 20: Extended Mode Register ................................................................................................................ 56
Figure 21: Status Read Register Timing ........................................................................................................... 58
Figure 22: Status Register Definition .............................................................................................................. 59
Figure 23: READ Burst ................................................................................................................................... 62
Figure 24: Consecutive READ Bursts .............................................................................................................. 63
Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 64
Figure 26: Random Read Accesses .................................................................................................................. 65
Figure 27: Terminating a READ Burst ............................................................................................................. 66
Figure 28: READ-to-WRITE ............................................................................................................................ 67
Figure 29: READ-to-PRECHARGE .................................................................................................................. 68
Figure 30: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x16) .................................................... 69
Figure 31: Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window (x32) .................................................... 70
Figure 32: Data Output Timing –
t
AC and
t
DQSCK .......................................................................................... 71
Figure 33: Data Input Timing ......................................................................................................................... 73
Figure 34: Write – DM Operation .................................................................................................................... 74
Figure 35: WRITE Burst ................................................................................................................................. 75
Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 76
Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 76
Figure 38: Random WRITE Cycles .................................................................................................................. 77
Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 78
Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 79
Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 80
Figure 42: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 81
Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 82
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 83
Figure 45: Bank Read – With Auto Precharge ................................................................................................... 86
Figure 46: Bank Read – Without Auto Precharge .............................................................................................. 87
Figure 47: Bank Write – With Auto Precharge .................................................................................................. 88
Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 89
Figure 49: Auto Refresh Mode ........................................................................................................................ 90
Figure 50: Self Refresh Mode .......................................................................................................................... 92
09005aef8541eee0
t89m_auto_lpddr.pdf - Rev. I 05/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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