512Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
• V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V (DDR400)
1
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
–
64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
•
t
RAS lockout supported (
t
RAP =
t
RCD)
Options
• Configuration
–
128 Meg x 4 (32 Meg x 4 x 4 banks)
–
64 Meg x 8 (16 Meg x 8 x 4 banks)
–
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic package
–
66-pin TSOP
–
66-pin TSOP (Pb-free)
–
60-ball FBGA (10mm x 12.5mm)
–
60-ball FBGA (10mm x 12.5mm) (Pb-free)
–
60-ball FBGA (8mm x 12.5mm)
–
60-ball FBGA (8mm x 12.5mm) (Pb-free)
• Timing – cycle time
–
5ns @ CL = 3 (DDR400)
–
6ns @ CL = 2.5 (DDR333) (FBGA only)
–
6ns @ CL = 2.5 (DDR333) (TSOP only)
• Self refresh
–
Standard
–
Low-power self refresh
• Temperature rating
–
Commercial (0°C to +70°C)
–
Industrial (–40°C to +85°C)
• Revision
–
x4, x8, x16
–
x4, x8, x16
Marking
128M4
64M8
32M16
TG
P
FN
2
BN
2
CV
3
CY
3
-5B
-6
2
-6T
2
None
L
None
IT
:F
:J
Notes: 1. DDR400 devices operating at < DDR333
conditions can use V
DD
/V
DDQ
= 2.5V +0.2V.
2. Available only on Revision F.
3. Available only on Revision J.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
Speed
Grade
-5B
-6
6T
-75E/-75Z
-75
Clock Rate (MHz)
CL = 2
133
133
133
133
100
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
Data-Out
Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
0.40ns
0.40ns
0.45ns
0.50ns
0.50ns
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512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Features
Table 2:
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Addressing
128 Meg x 4
32 Meg x 4 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
4K (A0–A9, A11, A12)
64 Meg x 8
16 Meg x 8 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0-A9, A11)
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
Table 3:
Marking
-5B
1
-6
-6T
-75E
-75Z
-75
Speed Grade Compatibility
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2)
Yes
–
–
–
–
–
-5B
Notes:
Yes
Yes
Yes
–
–
–
-6/-6T
Yes
Yes
Yes
Yes
–
–
-75E
Yes
Yes
Yes
Yes
Yes
–
-75Z
Yes
Yes
Yes
Yes
Yes
Yes
-75
Yes
Yes
Yes
Yes
Yes
Yes
-75
1. The -5B device is backward compatible with all slower speed grades. The voltage range of
-5B device operating at slower speed grades is V
DD
= V
DDQ
= 2.5V ± 0.2V.
Figure 1:
512Mb DDR SDRAM Part Numbers
Example Part Number: MT46V32M16P-6T:F
-
MT46V
Configuration
Package
Speed
:
Sp.
Op. Temp. Revision
Revision
:F x4, x8, x16
:J x4, x8, x16
Configuration
128 Meg x 4
64 Meg x 8
32 Meg x 16
Package
400-mil TSOP
400-mil TSOP (Pb-free)
10mm x 12.5mm FBGA
10mm x 12.5mm FBGA (Pb-free)
8mm x 12.5mm FBGA
8mm x 12.5mm FBGA (Pb-free)
TG
P
FN
BN
CV
CY
-5B
-6
-6T
Speed Grade
tCK = 5ns, CL = 3
tCK = 6ns, CL = 2.5
tCK = 6ns, CL = 2.5
128M4
64M8
32M16
IT
Operating Temp
Commercial
Industrial
Special Options
Standard
L
Low power
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA Part Marking Decoder on Micron’s Web site:
www.micron.com.
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512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Table of Contents
Table of Contents
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin and Ball Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Specifications – I
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
ACTIVE (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
PRECHARGE (PRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
BURST TERMINATE (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AUTO REFRESH (AR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
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512Mb_DDRTOC.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
Power
applied
Power
on
PRE
Precharge
all banks
LMR
Self
refresh
REFS
LMR
REFSX
Idle
REFA
all banks
precharged
CKEL
CKEH
MR
EMR
Auto
refresh
Active
power-
down
ACT
CKE HIGH
Precharge
power-
down
CKE LOW
Row
active
WRITE
WRITE
WRITE A
Write
READ A
READ
READ
BST
READ
Burst
stop
Read
WRITE A
PRE
READ A
PRE
PRE
READ A
Write A
Read A
PRE
Precharge
PREALL
Automatic sequence
Command sequence
ACT = ACTIVE
BST = BURST TERMINATE
CKEH = Exit power-down
CKEL = Enter power-down
EMR = Extended mode register
LMR = LOAD MODE REGISTER
MR = Mode register
PRE = PRECHARGE
PREALL = PRECHARGE all banks
READ A = READ with auto precharge
REFA = AUTO REFRESH
REFS = Enter self refresh
REFSX = Exit self refresh
WRITE A = WRITE with auto precharge
Note:
This diagram represents operations within a single bank only and does not capture concur-
rent operations in other banks.
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DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Functional Description
Functional Description
The DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an inter-
face designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and two corresponding
n-bit-wide,
one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which may then
be followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8
locations. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All
inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs
are SSTL_2, Class II compatible.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper
byte. For the lower byte (DQ[7:0]) DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ[15:8]) DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
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DDR_x4x8x16_Core1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
