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MT47H256M4HQ-25EIT

256MX4 DDR DRAM, 0.35ns, PBGA60, 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60

器件类别:存储    存储   

厂商名称:Micron Technology

厂商官网:http://www.mdtic.com.tw/

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Micron Technology
零件包装代码
BGA
包装说明
TFBGA,
针数
60
Reach Compliance Code
compliant
访问模式
MULTI BANK PAGE BURST
最长访问时间
0.35 ns
其他特性
AUTO/SELF REFRESH
JESD-30 代码
R-PBGA-B60
JESD-609代码
e1
长度
11.5 mm
内存密度
1073741824 bit
内存集成电路类型
DDR DRAM
内存宽度
4
功能数量
1
端口数量
1
端子数量
60
字数
268435456 words
字数代码
256000000
工作模式
SYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
256MX4
封装主体材料
PLASTIC/EPOXY
封装代码
TFBGA
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)
260
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
1.9 V
最小供电电压 (Vsup)
1.5 V
标称供电电压 (Vsup)
1.55 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN SILVER COPPER
端子形式
BALL
端子节距
0.8 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
30
宽度
8 mm
文档预览
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Features
DDR2 SDRAM
MT47R256M4 – 32 Meg x 4 x 8 banks
MT47R128M8 – 16 Meg x 8 x 8 banks
MT47R64M16 – 8 Meg x 16 x 8 banks
Features
V
DD
/V
DDQ
= +1.55V, 1.5–1.9V range
Backward compatible with 1.8V DDR2
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS compliant
Supports JEDEC clock jitter specification
Very low power operation
Options
1
Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks)
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
FBGA package (Pb-free) – x16
84-ball FBGA (8mm x 12.5mm) Rev. G
FBGA package (Pb-free) – x4, x8
60-ball FBGA (8mm x 11.5mm) Rev. G
Timing – cycle time
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 4 (DDR2-667)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C;
–40°C
T
A
85°C)
Automotive (–40°C
T
C
, T
A
105ºC)
Revision
Note:
Marking
256M4
128M8
64M16
HR
HQ
-25E
-25
-3E
-3
-37E
None
IT
AT
:G
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed Grade
-25E
-25
-3E
-3
-37E
CL = 3
400
400
400
400
400
CL = 4
533
533
667
533
533
CL = 5
800
667
667
667
n/a
CL = 6
800
800
n/a
n/a
n/a
CL = 7
n/a
n/a
n/a
n/a
n/a
t
RC
(ns)
55
55
54
55
55
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
256 Meg x 4
32 Meg x 4 x 8 banks
8K
A[13:0] (16K)
BA[2:0] (8)
A[11, 9:0] (2K)
128 Meg x 8
16 Meg x 8 x 8 banks
8K
A[13:0] (16K)
BA[2:0] (8)
A[9:0] (1K)
64 Meg x 16
8 Meg x 16 x 8 banks
8K
A[12:0] (8K)
BA[2:0] (8)
A[9:0] (1K)
Figure 1: 1Gb DDR2 Part Numbers
Example Part Number: MT47H128M8HQ-37E
-
MT47H
Configuration
Package
Speed
:
Revision
{
:G
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
Package
Pb-free
84-ball 8mm x 12.5mm FBGA
60-ball 8mm x 11.5mm FBGA
HR
HQ
256M4
128M8
64M16
Speed Grade
-25E
-25
-3E
-3
-37E
tCK = 2.5ns, CL = 5
tCK = 2.5ns, CL = 6
tCK = 3ns, CL = 4
tCK = 3ns, CL = 5
tCK = 3.75ns, CL = 4
Revision
IT Industrial temperature
AT Automotive temperature
Note:
1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
State Diagram .................................................................................................................................................. 8
Functional Description ..................................................................................................................................... 9
Industrial Temperature ................................................................................................................................ 9
Automotive Temperature ........................................................................................................................... 10
General Notes ............................................................................................................................................ 10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 14
Packaging ...................................................................................................................................................... 18
Package Dimensions .................................................................................................................................. 18
FBGA Package Capacitance ......................................................................................................................... 21
Electrical Specifications – Absolute Ratings ..................................................................................................... 22
Temperature and Thermal Impedance ........................................................................................................ 22
Electrical Specifications – I
DD
Parameters ........................................................................................................ 24
I
DD
Specifications and Conditions ............................................................................................................... 24
I
DD7
Conditions .......................................................................................................................................... 25
AC Timing Operating Specifications ................................................................................................................ 29
AC and DC Operating Conditions .................................................................................................................... 38
ODT DC Electrical Characteristics ................................................................................................................... 39
Input Electrical Characteristics and Operating Conditions ............................................................................... 40
Output Electrical Characteristics and Operating Conditions ............................................................................. 43
Output Driver Characteristics ......................................................................................................................... 45
Power and Ground Clamp Characteristics ....................................................................................................... 49
AC Overshoot/Undershoot Specification ......................................................................................................... 50
Input Slew Rate Derating ................................................................................................................................ 52
Commands .................................................................................................................................................... 65
Truth Tables ............................................................................................................................................... 65
DESELECT ................................................................................................................................................. 69
NO OPERATION (NOP) .............................................................................................................................. 70
LOAD MODE (LM) ..................................................................................................................................... 70
ACTIVATE .................................................................................................................................................. 70
READ ......................................................................................................................................................... 70
WRITE ....................................................................................................................................................... 70
PRECHARGE .............................................................................................................................................. 71
REFRESH ................................................................................................................................................... 71
SELF REFRESH ........................................................................................................................................... 71
Mode Register (MR) ........................................................................................................................................ 71
Burst Length .............................................................................................................................................. 72
Burst Type ................................................................................................................................................. 73
Operating Mode ......................................................................................................................................... 73
DLL RESET ................................................................................................................................................. 73
Write Recovery ........................................................................................................................................... 74
Power-Down Mode .................................................................................................................................... 74
CAS Latency (CL) ........................................................................................................................................ 75
Extended Mode Register (EMR) ....................................................................................................................... 76
DLL Enable/Disable ................................................................................................................................... 77
Output Drive Strength ................................................................................................................................ 77
DQS# Enable/Disable ................................................................................................................................. 77
RDQS Enable/Disable ................................................................................................................................. 77
Output Enable/Disable ............................................................................................................................... 77
On-Die Termination (ODT) ........................................................................................................................ 78
Contents
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 78
Posted CAS Additive Latency (AL) ............................................................................................................... 78
Extended Mode Register 2 (EMR2) .................................................................................................................. 80
Extended Mode Register 3 (EMR3) .................................................................................................................. 81
Initialization .................................................................................................................................................. 82
ACTIVATE ...................................................................................................................................................... 86
READ ............................................................................................................................................................. 88
READ with Precharge ................................................................................................................................. 92
READ with Auto Precharge .......................................................................................................................... 94
WRITE ........................................................................................................................................................... 99
PRECHARGE ................................................................................................................................................. 109
REFRESH ...................................................................................................................................................... 110
SELF REFRESH .............................................................................................................................................. 111
Power-Down Mode ....................................................................................................................................... 113
Precharge Power-Down Clock Frequency Change .......................................................................................... 120
Reset ............................................................................................................................................................. 121
CKE Low Anytime ...................................................................................................................................... 121
ODT Timing .................................................................................................................................................. 123
MRS Command to ODT Update Delay ........................................................................................................ 125
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Table 1: Key Timing Parameters ...................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 16
Table 4: Input Capacitance ............................................................................................................................ 21
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 22
Table 6: Temperature Limits .......................................................................................................................... 23
Table 7: Thermal Impedance ......................................................................................................................... 23
Table 8: General I
DD
Parameters .................................................................................................................... 24
Table 9: I
DD7
Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 25
Table 10: DDR2 I
DD
Specifications and Conditions (Die Revision G) ................................................................ 26
Table 11: AC Operating Specifications and Conditions .................................................................................... 29
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 38
Table 13: ODT DC Electrical Characteristics ................................................................................................... 39
Table 14: Input DC Logic Levels ..................................................................................................................... 40
Table 15: Input AC Logic Levels ..................................................................................................................... 40
Table 16: Differential Input Logic Levels ........................................................................................................ 41
Table 17: Differential AC Output Parameters .................................................................................................. 43
Table 18: Output DC Current Drive ................................................................................................................ 43
Table 19: Output Characteristics .................................................................................................................... 44
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 45
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 46
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 47
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 48
Table 24: Input Clamp Characteristics ........................................................................................................... 49
Table 25: Address and Control Balls ............................................................................................................... 50
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 50
Table 27: AC Input Test Conditions ................................................................................................................ 51
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (
t
IS and
t
IH) ................................................... 53
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (
t
IS and
t
IH) .......................................... 54
Table 30: DDR2-400/533
t
DS,
t
DH Derating Values with Differential Strobe ..................................................... 57
Table 31: DDR2-667/800/1066
t
DS,
t
DH Derating Values with Differential Strobe ............................................ 58
Table 32: Single-Ended DQS Slew Rate Derating Values Using
t
DS
b
and
t
DH
b
.................................................. 59
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
REF
) at DDR2-667 ..................................... 59
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
REF
) at DDR2-533 ..................................... 60
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
REF
) at DDR2-400 ..................................... 60
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 65
Table 37: Truth Table – Current State Bank
n
– Command to Bank
n
............................................................... 66
Table 38: Truth Table – Current State Bank
n
– Command to Bank
m
.............................................................. 68
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 69
Table 40: Burst Definition .............................................................................................................................. 73
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 94
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 100
Table 43: Truth Table – CKE ......................................................................................................................... 115
List of Tables
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.
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