ADVANCE
‡
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
18Mb DDR SIO SRAM
2-Word Burst
FEATURES
• 18Mb Density (2 Meg x 8, 1 Meg x 18, 512K x 36)
• DLL circuitry for wide-output, data valid window
and future frequency scaling
• Separate independent read and write data ports
• DDR READ or WRITE operation initiated each cycle
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Optional-use Echo Clocks (CQ, CQ#) for flexible
receive data sychronization
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +1.8V core and HSTL I/O
• Clock-stop capability with
ms
restart
• 13x15mm, 1mm pitch, 11 x 15 grid FBGA package
• User programmable impedance output
• JTAG boundary scan
MT57W2MH8C
MT57W1MH18C
MT57W512H36C
165-BALL FBGA
GENERAL DESCRIPTION
The Micron
®
DDR separate I/O, synchronous,
pipelined, burst SRAM employs high-speed, low-power
CMOS designs using an advanced 6T CMOS process. The
architecture consists of two separate DDR (double data
rate) ports to access the memory array. The read port has
dedicated data outputs to support READ operations. The
write port has dedicated data inputs to support WRITE
operations. This architecture eliminates the need for high-
speed bus turnaround. Access to each port is accom-
plished using a common address bus. Addresses for reads
and writes are latched on rising edges of the K and K#
input clocks, respectively. Each address location is asso-
ciated with two words that burst sequentially into or out
of the device. Bus turnaround cycles are eliminated and
a new data transaction can be requested each clock cycle,
permitting higher request rates than DDR SRAMs with-
out separated input and output buses.
Depth expansion is accomplished with a single device
select (LD#) which is received at K rising edge. All syn-
chronous inputs pass through registers controlled by the
K or K# input clock rising edges. Active LOW byte writes
(BWx#) permit byte or nybble write selection. Write data
and byte writes are registered on the rising edges of both
K and K#. The addressing within each burst of two is fixed
and sequential, beginning with the lowest address and
ending with the highest one. All synchronous data out-
puts pass through output registers controlled by the ris-
OPTIONS
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
MARKING
-3
-3.3
-4
-5
-6
-7.5
MT57W2MH8C
MT57W1MH18C
MT57W512H36C
F
VALID PART NUMBERS
PART NUMBER
MT57W2MH8CF-xx
MT57W1MH18CF-xx
MT57W512H36CF-xx
DESCRIPTION
2 Meg x 8, DDR SIOb2 FBGA
1 Meg x 18, DDR SIOb2 FBGA
512K x 36, DDR SIOb2 FBGA
18Mb 1.8V V
DD
, HSTL, DDR SIO SRAM
MT57W1MH18C_3.p65 – Rev. 3, Pub. 12/01
1
©2001, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
‡
PRODUCTS
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
GENERAL DESCRIPTION (continued)
ing edges of the output clocks (C and C# if provided;
otherwise, K and K#).
Four pins are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK), and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs use
1.8V I/O levels to shift data during this testing mode of
operation.
The SRAM operates from a +1.8V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for applications that require a new trans-
action to be initiated each clock cycle.
Please refer to Micron’s Web site (www.micron.com/
sram)
for the latest data sheet.
Output tri-stating is automatically controlled so that the
bus is released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing gen-
eration. Back-to-back READ cycles can be initiated at
every K rising edge.
WRITE cycles are initiated by R/W# LOW and provid-
ing the address at K rising edge. Data is expected at the
rising edge of K and K#, beginning at the next K rising
edge after the cycle is initiated. Write registers are incor-
porated to facilitate pipelined self-timed WRITE cycles
and provide fully coherent data for all combinations of
reads and writes. A read can immediately follow a write
even if they are to the same address. Although the write
data has not been written to the memory array, the SRAM
will deliver the data from the write register instead of
using the older data from the memory array. The latest
data is always utilized for all bus transactions. WRITE
cycles can be initiated on every K rising edge.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst-of-two data, and require one full clock cycle of bus
utilization. Any transaction type can be initiated at K
rising edge independent of the previous transaction type.
This permits any random operation without ever need-
ing bus turnaround delays.
READ cycles are pipelined. The request is initiated by
driving R/W# HIGH and providing the address at K rising
edge. Data is delivered after the next rising edge of K,
using C and C# as the output timing references; or using
K and K#, if C and C# are tied HIGH. If C and C# are tied
HIGH, they may not be toggled during device operation.
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported except for x8
devices, in which nybble write is supported. The active
LOW write controls, BWx# (NWx#), are registered coinci-
dent with their corresponding data. This feature can elimi-
nate the need for some READ-MODIFY-WRITE cycles,
collapsing it to a single BYTE/NYBBLE WRITE operation
in some instances.
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
n
ADDRESS
LD#
R/W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
R/W#
BW0#
BW1#
D (Data In)
LD#
K
K#
18
DATA
REGISTRY
& LOGIC
36
WR
RE
I G
T
E 2
WD
RR
I I
T V
EE
R
2
n
x 36
MEMORY
ARRAY
S
EA
NM
SP
ES
36
MUX
RO
EU
GT
P
U
A
T
C
C,C#
OR
K,K#
36
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
18
Q
(Data Out)
2
K
CQ
CQ#
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information. The x8 and x36 operation is the same, with appropriate adjustments of depth and
width.
2. n = 19
18Mb 1.8V V
DD
, HSTL, DDR SIO SRAM
MT57W1MH18C_3.p65 – Rev. 3, Pub. 12/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The QDR SRAM is equipped with programmable im-
pedance output buffers. This allows a user to match the
driver impedance to the system. To adjust the imped-
ance, an external precision resistor (RQ) is connected
between the ZQ pin and V
SS
. The value of the resistor
must be five times the desired impedance. For example,
a 350W resistor is required for an output impedance of
70W. To ensure that output impedance is one fifth the
value of RQ (within 10 percent), the range of RQ is 175W
to 350W. Alternately, the ZQ pin can be connected di-
rectly to V
DD
, which will place the device in a minimum
impedance mode.
Output impedance updates may be required because,
over time, variations may occur in supply voltage and
temperature. The device samples the value of RQ. An
update of the impedance is transparent to the system.
Impedance updates do not affect device operation, and
all data sheet timing and current specifications are met
during an update.
The device will power up with an output impedance
set at 50W. To guarantee optimum output driver imped-
ance after power-up, the SRAM needs 1,024 cycles to
update the impedance. The user can operate the part
with fewer than 1,024 clock cycles, but optimal output
impedance is not guaranteed.
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry auto-
matically resets the DLL when the absence of input clock
is detected. See Micron Technical Note TN-54-02 for
more information on clock DLL start-up procedures.
Optional-use echo clocks are provided to precisely
indicate data validity. Data changes occur very near to
the rising edges of CQ and CQ#.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock pair
by tying C and C# HIGH. In this mode the SRAM will use
K and K# in place of C and C#. This mode provides the
most rapid data output but does not compensate for
system clock skew and flight times.
DEPTH EXPANSION
Depth expansion is easily done by providing a new
LD# signal for each bank. R/W# can be shared among all
SRAMs in the system if driver fanout permits.
APPLICATION EXAMPLE
SRAM #1
Vt
R
D
SA0:n
B
W
R W x
# # #
ZQ
Q
C C# K K#
R = 250Ω
D
SA0:n
SRAM #4
B
W
R W x
# # #
ZQ
Q
C C# K K#
R = 250Ω
DATA IN 0:71
DATA OUT 0:71
Address
Read#
BUS
Write#
MASTER
BW0:7#
R
Vt
Vt
(CPU
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
/2
NOTE:
In this approach, the second clock pair drives the C and C# clocks, but is delayed such that return data meets data setup
and hold times at the bus master.
18Mb 1.8V V
DD
, HSTL, DDR SIO SRAM
MT57W1MH18C_3.p65 – Rev. 3, Pub. 12/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
2 MEG x 8 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
SA
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
SA
4
R/W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
NW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
NW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
*Expansion addresses: 10A for 36Mb, 2A for 72Mb.
NOTE:
NW0# controls writes to D0:D3. NW1# controls writes to D4:D7.
18Mb 1.8V V
DD
, HSTL, DDR SIO SRAM
MT57W1MH18C_3.p65 – Rev. 3, Pub. 12/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
1 MEG x 18 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA*
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
SA
4
R/W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
BW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
BW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
*Expansion addresses: 3A for 36Mb, 10A for 72Mb, 2A for 144Mb.
NOTE:
BW0# controls writes to D0:D8. BW1# controls writes to D9:D17.
18Mb 1.8V V
DD
, HSTL, DDR SIO SRAM
MT57W1MH18C_3.p65 – Rev. 3, Pub. 12/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ARM技术
