AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
256K x 4 SRAM
SRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD-883
256K x 4 SRAM
PIN ASSIGNMENT (Top View)
28-Pin DIP
(400 MIL)
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
OE
Vss
FEATURES
High speed: 15, 20, 25, 35 and 45ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
• Single +5V (±10%) power supply
• Easy memory expansion with
/
C
/
E and
/
O
/
E options
• All inputs and outputs are TTL compatible
•
•
•
•
32-Pin LCC
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
OPTIONS
• Timing
15ns access (Contact factory)
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Packages
Ceramic DIP (400 mil)
Ceramic Flat Pack
Ceramic LCC
Ceramic SOJ
Ceramic Quad LCC (Contact factory)
MARKING
-15
-20
-25
-35
-45
-55*
-70*
C
F
EC
DCJ
ECW
L
E
No. 109
No. 303
No. 207
No. 501
No. 206
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
OE
Vss
32-Pin Flat Pack
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
32-Pin LCC
A7
A9
A12
A8
A14
A7
NC
NC
Vcc
V
CC
WE
A6
A13
A5
4 3 2 1 32 31 30
A6
A10
5
A11
A5
A11
6
A12
A4
A12
7
A13
A3
A13
8
A14
A2
A14
9
A15
A1
A16
N15
10
A0
A17
A16
11
NC
CE
A17
12
DQ1
OE
13
CE
14 15 16 17 18 19 20
A2
A8
29
A2
A4
A9
28
A4
A3
A11
27
A3
A1
NC
26
A1
A0
OE
25
NC
NC
A10
24
NC
CE
23
A0
NC
DQ8
22
NC
NC
DQ7
21
DQ4
• 2V data retention, low power standby
• Radiation Tolerant (Epi)
*Electrical characteristics identical to those provided for the 45ns
access devices.
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs high-
speed, low-power CMOS designs using a four transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon tech-
nology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (/C
/
E) and output en-
able (?O
/
E) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system
design. Writing to these devices is accomplished when
MT5C1005 883C
REV. 11/97
DS000005
write enable (
?
W
/
E) and
/
C
/
E inputs are both LOW. Reading
is accomplished when
/
W
/
E remains HIGH while
/
C
/
E and
?
O
/
E go LOW. The devices offer a reduced power standby
mode when disabled. This allows system designs to achieve
low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the stan-
dard version.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
1-57
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
DQ2
NC
DQ3
OE
Vss
V
SS
NC
WE
DQ4
DQ1
DQ5
DQ2
DQ6
DQ3
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
256K x 4 SRAM
FUNCTIONAL BLOCK DIAGRAM
Vcc
GND
A
A
DQ4
A
ROW DECODER
A
A
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
DQ1
A
CE
A
A
(LSB)
OE
WE
COLUMN DECODER
(LSB)
POWER
POWER
DOWN
A
A
A
A
A
A
A
A
A
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
/
O
/
E
X
L
H
X
/
C
/
E
H
L
L
L
?
W
/
E
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C1005 883C
REV. 11/97
DS000005
1-58
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative to Vss .. -.5V to Vcc+.5V
Voltage on V
CC
Supply Relative to Vss ............ -.5V to +7V
Storage Temperature ................................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current .........................................
±20
Lead Temperature (soldering 10 seconds) .............. +260°C
Junction Temperature ................................................ +175°C
MT5C1005 883C
256K x 4 SRAM
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C
≤
T
C
≤
125°C; Vcc = 5.0V
±
10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V
≤
V
IN
≤
V
CC
Output(s) Disabled
0V
≤
V
OUT
≤
V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYMBOL
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MAX
DESCRIPTION
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
/
C
/
E
≤
V
IL
; V
CC
= MAX
f = MAX = 1/
t
RC (MIN)
Output Open
/
C
/
E
≥
V
IH
; V
CC
= MAX
f = MAX = 1/
t
RC (MIN)
Output Open
/
C
/
E
≥
V
IH
, All Other Inputs
≤
V
IL
or
≥
V
IH
, V
CC
= MAX
f = 0 Hz
/
C
/
E
≥
V
CC
-0.2V; V
CC
= MAX
V
IL
≤
V
SS
+0.2V
V
IH
≥
V
CC
-0.2V; f = 0 Hz
“L” Version Only
SYMBOL
I
CC
-15
170
-20
155
-25
140
-35
125
-45
115
UNITS
mA
NOTES
3
MIN
2.2
-0.5
-5
-5
2.4
0.4
MAX
V
CC
+0.5
0.8
5
5
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1, 2
I
SBT1
65
50
45
40
35
mA
I
SBT2
25
25
25
25
25
mA
I
SBC2
I
SBC2
10
5
10
5
10
5
10
5
10
5
mA
mA
CAPACITANCE
DESCRIPTION
Input Capacitance (A0-A2, A12-A15)
Output Capacitance (DQ1-DQ4)
Input Capacitance (All Other Inputs)
MT5C1005 883C
REV. 11/97
DS000005
CONDITIONS
T
A
= 25°C, f = 1MHz
V
CC
= 5V
SYMBOL
C
I
C
O
C
I
MIN
MAX
10
8
8
UNITS
pF
pF
pF
NOTES
4
4
4
1-59
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
256K x 4 SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55°C
≤
T
C
≤
125°C; V
CC
= 5V
±
10%)
-15
-20
MAX
MIN
MAX
MIN
-25
MAX
MIN
-35
MAX
MIN
-45
MAX
UNITS NOTES
DESCRIPTION
SYM
READ Cycle
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE Cycle
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
MIN
15
15
15
3
3
6
0
15
6
0
5
20
20
20
3
3
8
0
20
7
0
7
25
25
25
3
3
10
0
25
8
0
9
35
35
35
3
3
15
0
35
12
0
12
45
45
45
3
3
15
0
45
12
0
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4
4
4, 6, 7
15
12
12
0
1
12
7
0
3
0
7
20
15
15
0
1
15
8
0
3
0
9
25
17
17
0
1
17
10
0
3
0
10
35
20
20
0
1
20
13
0
3
0
13
45
20
20
0
1
20
13
0
3
0
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
MT5C1005 883C
REV. 11/97
DS000005
1-60
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
256K x 4 SRAM
+5V
480
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
Q
255
+5V
480
Q
255
5 pF
30 pF
Fig. 1 OUTPUT LOAD
EQUIVALENT
Fig. 2 OUTPUT LOAD
EQUIVALENT
NOTES
1. All voltages referenced to V
SS
(GND).
2. -3V for pulse width < 20ns.
3. I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
1
unloaded, and f = ————— Hz
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
LZCE,
t
LZOE,
t
LZWE
, t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5 pF as in Fig. 2. Transition is
measured
±
200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE and
t
HZWE is less than
t
LZWE, and
t
LZOE is less than
t
HZOE.
8.
?
W
/
E is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
11.
t
RC = READ cycle time.
12. Chip enable (/C
/
E) and write enable (?W
/
E) can initiate
and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
/
C
/
E
≥
(V
CC
- 0.2V) V
CC
= 2V
V
IN
≥
(V
CC
- 0.2V)
or
≤
0.2V
V
CC
= 3V
CONDITIONS
SYMBOL
V
DR
I
CCDR
MIN
2
TYP
MAX
—
1.0
2.0
t
CDR
t
R
UNITS
V
mA
mA
ns
ns
NOTES
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
t
RC
—
4
4, 11
,
,,
,
Vcc
CE
V IH
V IL
MT5C1005 883C
REV. 11/97
DS000005
LOW V
CC
DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
VDR >2V
tCDR
VDR
1-61
,
,,,
,
,,
,,
,,
4.5V
tR
DON’T CARE
UNDEFINED
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
