MT9044
T1/E1/OC3 System Synchronizer
Data Sheet
Features
•
Supports AT&T TR62411 and Bellcore GR-1244-
CORE Stratum 3, Stratum 4 Enhanced and
Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048
kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1,544
kbit/s interfaces and 2,048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different 8KHz framing pulses
Holdover frequency accuracy of 0.05 PPM
Holdover indication
Attenuates wander from 1.9Hz
•
•
•
Ordering Information
MT9044AP
MT9044AL
44 Pin PLCC
44 Pin MQFP
November 2003
•
•
•
•
•
-40°C to +85°C
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
Applications
•
•
Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
•
•
•
•
OSCi
OSCo
TCLR
VDD
VSS
Master Clock
TCK
TDI
TMS
TRST
TDO
PRI
SEC
IEEE
1149.1a
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Output
Interface
Circuit
Reference
Select
MUX
Reference
Select
Selected
Reference
State
Select
Input
Impairment
Monitor
TIE
Corrector
Enable
State
Select
C19o
C1.5o
C3o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Feedback
RSEL
LOS1
LOS2
Automatic/Manual
Control State Machine
Guard Time
Circuit
Frequency
Select
MUX
APLL
ACKo
ACKi
MS1
MS2
RST HOLDOVER
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
MT9044
Description
Data Sheet
The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz,
or 8kHz input reference.
The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander
tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency and MTIE requirements for these specifications.
PRI
SEC
TRST
TCLR
TCK
VSS
TMS
RST
TDI
FS1
FS2
6 5 4 3 2 1 44 43 42 41 40
PRI
SEC
TRST
TCLR
TCLK
VSS
TMS
RST
TDI
FS1
FS2
44 43 42 41 40 39 38 37 36 35 34
39
38
37
36
35
34
33
32
31
30
29
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
7
8
9
10
11
12
13
14
15
16
17
MT9044AP
IC
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
VDD
OSCo
OSCi
VSS
F16o
RSP
F0o
TSP
F8o
C1.5o
AVDD
1
2
3
4
5
6
7
8
9
10
11
MT9044AL
33
32
31
30
29
28
27
26
25
24
23
IC
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
VSS
GTi
HOLDOVER
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
C3o
C2o
C4o
C19o
Figure 2 - Pin Connections
2
Zarlink Semiconductor Inc.
C3o
C2o
C4o
C19o
ACKi
VSS
ACKo
C8o
C16o
C6o
VDD
MT9044
Pin Description
Pin # Pin #
PLCC MQFP
1,10, 39,4,17
23,31
,25
2
3
40
41
Name
V
SS
TCK
TCLR
Ground.
0 Volts.
Description
Data Sheet
Test Clock (TTL Input):
Provides the clock to the JTAG test logic. This pin is
internally pulled up to V
DD
.
TIE Circuit Reset (TTL Input):
A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300ns. This pin is internally pulled down to VSS.
Test Reset (TTL Input):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
Secondary Reference (TTL Input).
This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of
the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi
control inputs (Automatic or Manual). This pin is internally pulled up to V
DD
.
Primary Reference (TTL Input).
See pin description for SEC. This pin is
internally pulled up to V
DD
.
Positive Supply Voltage.
+5V
DC
nominal.
Oscillator Master Clock (CMOS Output).
For crystal operation, a 20MHz
crystal is connected from this pin to OSCi, see Figure 10. For clock oscillator
operation, this pin is left unconnected, see Figure 9.
Oscillator Master Clock (CMOS Input).
For crystal operation, a 20MHz crystal
is connected from this pin to OSCo, see Figure 10. For clock oscillator operation,
this pin is connected to a clock source, see Figure 9.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output).
This is an 8kHz 61ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
Receive Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output).
This is an 8kHz 244ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.
Transmit Sync Pulse (CMOS Output).
This is an 8kHz 488ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
Frame Pulse (CMOS Output).
This is an 8kHz 122ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
Clock 1.544MHz (CMOS Output).
This output is used in T1 applications.
Analog Vdd.
+5V
DC
nominal.
Clock 3.088MHz (CMOS Output).
This output is used in T1 applications.
4
5
42
43
TRST
SEC
6
7,28
8
44
1,22
2
PRI
V
DD
OSCo
9
3
OSCi
11
5
F16o
12
6
RSP
13
7
F0o
14
8
TSP
15
16
17
18
9
10
11
12
F8o
C1.5o
AVDD
C3o
3
Zarlink Semiconductor Inc.
MT9044
Pin Description (continued)
Pin # Pin #
PLCC MQFP
19
20
21
22
24
25
26
27
29
30
13
14
15
16
18
19
20
21
23
24
Name
C2o
C4o
C19o
ACKi
ACKo
C8o
C16o
C6o
Description
Data Sheet
Clock 2.048MHz (CMOS Output).
This output is used for ST-BUS operation at
2.048Mb/s.
Clock 4.096MHz (CMOS Output).
This output is used for ST-BUS operation at
2.048Mb/s and 4.096Mb/s.
Clock 19.44MHz (CMOS Output).
This output is used in OC3/STS3 applications.
Analog PLL Clock Input (CMOS Input).
This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
Analog PLL Clock Output (CMOS Output).
This output clock is generated by
the internal analog PLL.
Clock 8.192MHz (CMOS Output).
This output is used for ST-BUS operation at
8.192Mb/s.
Clock 16.384MHz (CMOS Output).
This output is used for ST-BUS operation
with a 16.384MHz clock.
Clock 6.312 Mhz (CMOS Output).
This output is used for DS2 applications.
HOLDOVER
Holdover (CMOS Output).
This output goes to a logic high whenever the digital
PLL goes into holdover mode.
GTi
Guard Time (Schmitt Input).
This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode, and
Primary Holdover Mode and Secondary Normal Mode. The logic level at this input
is gated in by the rising edge of F8o. See Tables 4 and 5.
Guard Time (CMOS Output).
The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input
through an RC circuit.
Secondary Reference Loss (TTL Input).
This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
Primary Reference Loss (TTL Input).
Typically, external equipment applies a
logic high to this input when the PRI reference signal is lost or invalid. The logic
level at this input is gated in by the rising edge of F8o. See LOS2 description. This
pin is internally pulled down to VSS.
Test Serial Data Out (TTL Output).
JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enabled.
Mode/Control Select 2 (TTL Input).
This input, in conjunction with MS1,
determines the device’s mode (Automatic or Manual) and state (Normal, Holdover
or Freerun) of operation. The logic level at this input is gated in by the rising edge
of F8o. See Table 3.
32
26
GTo
33
27
LOS2
34
28
LOS1
35
29
TDO
36
30
MS2
4
Zarlink Semiconductor Inc.
MT9044
Pin Description (continued)
Pin # Pin #
PLCC MQFP
37
31
Name
MS1
Description
Data Sheet
Mode/Control Select 1 (TTL Input).
The logic level at this input is gated in by
the rising edge of F8o. See pin description for MS2. This pin is internally pulled
down to VSS.
Reference Source Select (TTL Input).
In Manual Control, a logic low selects the
PRI (primary) reference source as the input reference signal and a logic high
selects the SEC (secondary) input. In Automatic Control, this pin must be at logic
low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
This pin is internally pulled down to VSS.
Internal Connection.
Tie low for normal operation.
Frequency Select 2 (TTL Input).
This input, in conjunction with FS1, selects
which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input
to the PRI and SEC inputs. See Table 1.
Frequency Select 1 (TTL Input).
See pin description for FS2.
Test Serial Data In (TTL Input).
JTAG serial test instructions and data are shifted
in on this pin. This pin is internally pulled up to V
DD
.
Reset (Schmitt Input).
A logic low at this input resets the MT9044. To ensure
proper operation, the device must be reset after changes to the method of control,
reference signal frequency changes and power-up. The RST pin should be held
low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs
are at logic high. Following a reset, the input reference source and output clocks
and frame pulses are phase aligned as shown in Figure 19.
Test Mode Select (TTL Input).
JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
.
38
32
RSEL
39
40
33
34
IC
FS2
41
42
43
35
36
37
FS1
TDI
RST
44
38
TMS
Functional Description
The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 shows the functional block diagram which is described in the following sections.
Reference Select MUX Circuit
The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables
1, 4 and 5.
Frequency Select MUX Circuit
The MT9044 operates with one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The
frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference
inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be
performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and
must not be used. See Table 1.
5
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