256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
DDR SDRAM
SMALL-OUTLINE DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Supports ECC error detection and correction
• Fast data transfer rates: PC3200
• Utilizes 400 MT/s DDR SDRAM components
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB
(128 Meg x 72)
• V
DD
= V
DD
Q = +2.6V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT9VDDT3272H – 256MB,
MT9VDDT6472H – 512MB,
MT9VDDT12872H – 1GB (ADVANCE
‡
)
For the latest data sheet, please refer to the Micron
®
Web
site:
www.micron.com/products/modules
Figure 1: 200-Pin SODIMM (MO-224)
1.25in. (31.75mm)
OPTIONS
MARKING
• Operating Temperature Range
Commercial (0°C
≤
T
A
≤
+70°C)
None
Industrial (-40°C
≤
T
A
≤
+85°C)
I
2
• Package
200-pin SODIMM (standard)
G
200-pin SODIMM (lead-free)
Y
2
• Memory clock, Speed, CAS Latency
1
5.0ns (200 MHz), 400 MT/s, CL = 3
-40B
• PCB
1.25in. (31.75mm)
See page 2 note
NOTE:
1. CL = Device CAS (READ) Latency.
2. Consult Micron for product availability.
Table 1:
Address Table
256MB
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
1Gb (128 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
1
©2005 Micron Technology, Inc. All rights reserved.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
256MB
256MB
512MB
512MB
1GB
1GB
CONFIGURATION
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
128 Meg x 72
128 Meg x 72
MODULE
BANDWIDTH
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
MEMORY CLOCK/
DATA RATE
5.0ns/400 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
PART NUMBER
MT9VDDT3272H(I)G-40B__
MT9VDDT3272H(I)Y-40B__
MT9VDDT6472H(I)G-40B__
MT9VDDT6472H(I)Y-40B__
MT9VDDT12872H(I)G-40B__
MT9VDDT12872H(I)Y-40B__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDT6472HG-265A1.
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
Table 4:
Pin Assignment
(200-pin SODIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
V
REF
51
V
SS
101
A9
151 DQ42
3
V
SS
53
DQ19
103
Vss
153 DQ43
5
DQ0
55
DQ24
105
A7
155
V
DD
7
DQ1
57
V
DD
107
A5
157
V
DD
9
V
DD
A3
159
V
SS
59 DQ25
109
11
DQS0
61
DQS3
111
A1
161
V
SS
13
DQ2
63
V
SS
113
V
DD
163 DQ48
15
V
SS
65
DQ26
115
A10
165 DQ49
17
DQ3
67
DQ27
117
BA0
167
V
DD
19
DQ8
69
V
DD
119
WE#
169 DQS6
21
V
DD
71
CB0
121
S0#
171 DQ50
23
DQ9
73
CB1
123
NC/A13 173
V
SS
25
DQS1
75
V
SS
125
V
SS
175 DQ51
27
V
SS
77
DQS8
127 DQ32 177 DQ56
29
DQ10
79
CB2
129 DQ33
179
V
DD
31
DQ11
81
V
DD
131
V
DD
181 DQ57
33
V
DD
83
CB3
133 DQS4 183 DQS7
35
CK0
85
NC
135 DQ34
185
V
SS
37
CK0#
87
V
SS
137
V
SS
187 DQ58
39
V
SS
89
CK2
139 DQ35 189 DQ59
41
DQ16
91
CK2#
141 DQ40
191
V
DD
43
DQ17
93
V
DD
143
V
DD
193
SDA
45
V
DD
95
NC
145 DQ41
195
SCL
47
DQS2
97
NC
147 DQS5 197 V
DDSPD
49
DQ18
99
A12
149
V
SS
199
NC
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
V
REF
52
V
SS
102
A8
152 DQ46
4
V
SS
54
DQ23
104
V
SS
154 DQ47
6
DQ4
56
DQ28
106
A6
156
V
DD
8
DQ5
58
V
DD
108
A4
158 CK1#
10
V
DD
60
DQ29
110
A2
160
CK1
12
DM0
62
DM3
112
A0
162
V
SS
14
DQ6
64
V
SS
114
V
DD
164 DQ52
16
V
SS
66
DQ30
116
BA1
166 DQ53
18
DQ7
68
DQ31
118 RAS# 168
V
DD
20
DQ12
70
V
DD
120 CAS# 170 DM6
72
CB4
122
NC
172 DQ54
22
V
DD
24
DQ13
74
CB5
124
NC
174
V
SS
26
DM1
76
V
SS
126
V
SS
176 DQ55
28
V
SS
78
DM8
128 DQ36 178 DQ60
30
DQ14
80
CB6
130 DQ37
180
V
DD
32
DQ15
82
V
DD
132
V
DD
182 DQ61
34
V
DD
84
CB7
134 DM4 184 DM7
36
V
DD
86
NC
136 DQ38
186
V
SS
38
V
SS
88
V
SS
138
V
SS
188 DQ62
40
V
SS
90
V
SS
140 DQ39 190 DQ63
42
DQ20
92
V
DD
142 DQ44
192
V
DD
44
DQ21
94
V
DD
144
V
DD
194
SA0
46
V
DD
96
CKE0
146 DQ45
196
SA1
48
DM2
98
NC
148 DM5 198
SA2
50
DQ22
100
A11
150
V
SS
200
NC
Pin 123 is NC for 256MB and 512MB and A13 for 1GB.
Figure 2: Module Layout
Front View
Back View
U8
U1
U2
U3
U4
U5
U6
U7
U9
U10
PIN 1
(all odd pins)
PIN 199
PIN 200
(all even pins)
PIN 2
Indicates a V
DD
or V
DD
Q pin
Indicates a V
SS
pin
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
TYPE
Input
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
118, 119, 120
35, 37, 89, 91, 158, 160
96
CKE0
121
S0#
116, 117
99, 100, 101, 102, 105,
106, 107, 108, 109, 110,
111, 112, 115, 123
(1GB)
BA0, BA1
A0–A12
(256MB, 512MB)
A0–A13
(1GB)
11, 25, 47, 61, 77, 133, 147,
169, 183
12, 26, 48, 62, 78, 134, 148,
170, 184
DQS0–DQS8
DM0–DM8
71,72, 73, 74, 79,
80, 83, 84
5-8, 13-20, 23-24, 29-32,
41-44, 49-50, 53-56, 59-60,
65-68, 127-130, 135-136,
139-142, 145-146, 151-154,
163-166, 171-172, 175-178,
181-182, 187-190
CB0–CB7
DQ0–DQ63
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied.
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Input Bank Address: BA0, BA1 define to which device bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Input Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also
provide the op-code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register (mode register or
extended mode register) is loaded during the LOAD MODE
REGISTER command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Input/ Check Bits.
Output
Input/ Data I/Os: Data bus.
Output
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions (Continued)
SYMBOL
SCL
SA0–SA2
SDA
TYPE
Input
Input
Input/
Output
Supply
Supply
DESCRIPTION
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
SSTL_2 reference voltage.
Power Supply: +2.6V ±0.1V.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
195
194, 196, 198
193
1, 2
9-10, 21-22, 33-34, 36, 45-
46, 57-58, 69-70, 81-82, 92-
94, 113-114, 131-132, 143-
144, 155-157, 167-168, 17-
180, 191-192
3-4 15-16, 27-28, 38-40,
51-52, 63-64, 75-76, 87-88,
90, 103-104, 125-126, 137-
138, 149-150, 159, 161-
162, 173-174, 185-186
197
85, 95, 97, 122, 123
(256MB, 512MB), 199, 98,
124, 200
V
REF
V
DD
V
SS
Supply Ground.
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
—
No Connect: These pins should be left unconnected.
pdf: 09005aef811d6080, source: 09005aef806e057b
DDA9C32_64_128x72HG.fm - Rev. B 06/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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