128MB, 256MB, 512MB (x72, ECC, SR)
184-Pin DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
Features
• JEDEC-standard 184-pin dual in-line memory
module (DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333MT/s DDR SDRAM
components
• Supports ECC error detection and correction
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and
512MB (64 Meg x 72)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs (128MB), 7.8125µs (256MB, 512MB)
maximum average periodic refresh interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT9VDDT1672A – 128MB
MT9VDDT3272A – 256MB
MT9VDDT6472A – 512MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 184-Pin DIMM (MO-206)
1.25in. (31.75mm)
OPTIONS
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)
1
• Memory Clock, Speed, CAS Latency
2
6ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz ), 266 MT/s, CL = 2
7.5ns (133 MHz ), 266 MT/s, CL = 2.5
• Self Refresh
Standard
Low Power
• PCB
1.25in. (31.75mm)
NOTE:
MARKING
G
Y
-335
-262
1
-26A
1
-265
None
L
1. Contact Micron for product availability.
2. CL = CAS (READ) latency.
Table 1:
Address Table
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef808f912d, source: 09005aef808f8ccd
DD9C16_32_64x72AG.fm - Rev. C 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB (x72, ECC, SR)
184-Pin DDR SDRAM UDIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
MEMORY CLOCK/
DATA RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
PART NUMBER
MT9VDDT1672A(L)G-335__
MT9VDDT1672A(L)Y-335__
MT9VDDT1672A(L)G-262__
MT9VDDT1672A(L)Y-262__
MT9VDDT1672A(L)G-26A__
MT9VDDT1672A(L)Y-26A__
MT9VDDT1672A(L)G-265__
MT9VDDT1672A(L)Y-265__
MT9VDDT3272A(L)G-335__
MT9VDDT3272A(L)Y-335__
MT9VDDT3272A(L)G-262__
MT9VDDT3272A(L)Y-262__
MT9VDDT3272A(L)G-26A__
MT9VDDT3272A(L)Y-26A__
MT9VDDT3272A(L)G-265__
MT9VDDT3272A(L)Y-265__
MT9VDDT6472A(L)G-335__
MT9VDDT6472A(L)Y-335__
MT9VDDT6472A(L)G-262__
MT9VDDT6472A(L)Y-262__
MT9VDDT6472A(L)G-26A__
MT9VDDT6472A(L)Y-26A__
MT9VDDT6472A(L)G-265__
MT9VDDT6472A(L)Y-265__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDT3272AG-265A1.
pdf: 09005aef808f912d, source: 09005aef808f8ccd
DD9C16_32_64x72AG.fm - Rev. C 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR)
184-Pin DDR SDRAM UDIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
DD
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DM2
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
DM3
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DD
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DM8
A10
CB6
V
DD
CB7
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DD
S0#
NC
DM5
V
SS
DQ46
162 DQ47
163
NC
164
V
DD
165 DQ52
166 DQ53
167
NC
168
V
DD
169 DM6
170 DQ54
171 DQ55
172
V
DD
173
NC
174 DQ60
175 DQ61
176
V
SS
177 DM7
178 DQ62
179 DQ63
180
V
DD
181
SA0
182
SA1
183
SA2
184 V
DDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
94
DQ4
95
DQ5
96
V
DD
97
DM0
98
DQ6
99
DQ7
100
V
SS
101
NC
102
NC
103
NC
104
V
DD
105 DQ12
106 DQ13
107 DM1
108
V
DD
109 DQ14
110 DQ15
111
NC
112
V
DD
113
NC
114 DQ20
115
NC/A12
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DD
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
DD
DQ16
Pin 115 is No Connect (128MB), and A12 (256MB, 512MB).
Figure 2: 184-Pin DIMM Pinouts
FRONT VIEW
U10
U1
U2
U3
U4
U5
U6
U7
U8
U9
PIN 1
PIN 52
Indicates a V
DD
pin
PIN 53
Indicates a V
SS
pin
PIN 92
BACK VIEW
No Components This Side
PIN 184
PIN 145
PIN 144
PIN 93
pdf: 09005aef808f912d, source: 09005aef808f8ccd
DD9C16_32_64x72AG.fm - Rev. C 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR)
184-Pin DDR SDRAM UDIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
TYPE
Input
Input
DESCRIPTION
Command Inputs: WE#, RAS#, and CAS# (along with S#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of
CK#. Output data (DQs and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output
drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE is synchronous for all functions except
for disabling outputs, which is achieved asynchronously.
CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWERDOWN. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is
an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied and until CKE is first brought HIGH.
After CKE is brought HIGH, it becomes an SSTL_2 input
only.
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S# is registered HIGH. S# is considered
part of the command code.
Bank Addresses: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
Address Inputs: Sampled during the ACTIVE command
(row-address) and READ/WRITE command (column-
address, with A10 defining auto precharge) to select one
location out of the memory array in the respective device
device bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies
to one device bank (A10 LOW) or all device banks (A10
HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of the
presence- detect portion of the module.
Check bits.
Data Strobe: DQS0–DQS8, Output with READ data, input
with WRITE data. DQS is edge-aligned with READ data,
centered in WRITE data. Used to capture data.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
63, 65, 154
16, 17, 75, 76, 137, 138
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115
(256MB, 512MB),
118,
122, 125, 130, 141
A0–A11
(128MB)
A0–A12
(256MB, 512MB)
Input
92
SCL
Input
181, 182, 183
91
SA0–SA2
SDA
Input
Input/Output
44, 45, 49, 51, 134, 135,
142, 144
5, 14, 25, 36, 47, 56, 67, 78,
86
CB0–CB7
DQS0–DQS8
Input/Output
Input/Output
pdf: 09005aef808f912d, source: 09005aef808f8ccd
DD9C16_32_64x72AG.fm - Rev. C 9/04 EN
4
128MB, 256MB, 512MB (x72, ECC, SR)
184-Pin DDR SDRAM UDIMM
Table 5:
Pin Descriptions (Continued)
DM0–DM8
DQ0–DQ63
Input/Output
Input/Output
Data Mask: DQS9–DQS17 function as DM0–DM8 to mask
WRITE data when when HIGH.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
97, 107, 119, 129, 140, 149,
159, 169, 177
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40,
53, 55, 57, 60, 61, 64, 68,
69, 72, 73, 79, 80, 83, 84,
87, 88, 94, 95, 98, 99, 105,
106, 109, 110, 117, 121,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
1
7, 15, 22, 30, 38, 46, 54, 62,
70, 77, 85, 96, 104, 108,
112, 120, 128, 136, 143,
148, 156, 164, 168, 172, 180
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152,
160, 176
184
9, 10, 71, 82, 90, 101, 102,
103, 111, 113, 115 (128MB),
158, 163, 167, 173
V
REF
V
DD
, V
DD
Q
Supply
Supply
SSTL_2 reference voltage.
Power Supply: +2.5V +0.2V.
V
SS
Supply
Ground.
V
DDSPD
NC
Supply
—
Serial EEPROM positive power supply: +2.3V to +3.6V.
This supply is isolated from the V
DD
/V
DD
Q supply.
No Connects.
pdf: 09005aef808f912d, source: 09005aef808f8ccd
DD9C16_32_64x72AG.fm - Rev. C 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
FPGA/CPLD
