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32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Features

DDR4 SDRAM LRDIMM

MTA36ASF4G72LZ – 32GB

Features

• DDR4 functionality and operations supported as

defined in the component data sheet

• 288-pin, command/address/control registered, data

buffered dual in-line, load reduced memory module

(LRDIMM)

• Fast data transfer rates: PC4-2666, PC4-2400

• 32GB (4 Gig x 72)

• V

= 1.20V (NOM)

• V

= 2.5V (NOM)

• V

DDSPD

= 2.5V (NOM)

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Low-power auto self refresh (LPASR)

• On-die internal, adjustable, V

REFDQ

generation

• Dual-rank

• On-board I

C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• 16 internal banks; 4 groups of 4 banks each

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Multiplexed command, and address bus

• Terminated control, command and address bus

Table 1: Key Timing Parameters

Data Rate (MT/s)

Industry

Speed Nomen-

Grade clature

-2G6

-2G4

-2G3

-2G1

PC4-2666

PC4-2400

PC4-2133

CL =

20,

CL =

2666

–

Figure 1: 288-Pin LRDIMM (MO-309, R/C-B, R/C-

B1)

Module height: 31.25mm (1.23in)

Options

• Operating temperature

– Commercial (0°C

≤

OPER

≤

95°C)

• Package

– 288-pin DIMM (halogen-free)

• Frequency/CAS latency

– 0.75ns @ CL = 19 (DDR4-2666)

– 0.83ns @ CL = 17 (DDR4-2400)

Marking

None

-2G6

-2G3

CL =

2666

2400

–

CL =

2400

–

CL =

2133

2400

2133

CL =

2133

CL =

1866

CL = CL =

1866 1600

CL =

1600

CL =

1333

–

1333

–

RCD

CL = 9 (ns)

–

1333

–

1333

(ns)

46.16

45.32

46.16

46.5

14.16 14.16

13.32 13.32

14.16 14.16

13.5

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Features

Table 2: Addressing

Parameter

Row address

Column address

Device bank group address

Device bank address per group

Device configuration

Module rank address

32GB

128K A[16:0]

1K A[9:0]

4 BG[1:0]

4 BA[1:0]

8Gb (2 Gig x 4), 16 banks

2 CS_n[1:0]

Table 3: Part Numbers and Timing Parameters – 32GB Modules

Base device: MT40A2G4,

8Gb DDR4 SDRAM

Module

Part Number

Density

Configuration

MTA36ASF4G72LZ-2G6__

MTA36ASF4G72LZ-2G3__

Notes:

32GB

4 Gig x 72

Module

Bandwidth

21.3 GB/s

19.2 GB/s

Memory Clock/

Data Rate

0.75ns/2666 MT/s

0.83ns/2400 MT/s

Clock Cycles

(CL-

RCD-

RP)

19-19-19

17-17-17

1. The data sheet for the base device can be found on micron.com.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MTA36ASF4G72LZ-2G6D1.

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Pin Assignments

Table 4: Pin Assignments

288-Pin DDR4 LRDIMM Front

Symbol

DQ4

DQ0

DQS9_t

DQS09_c

DQ6

DQ2

DQ12

DQ8

DQS10_t

DQS10_c

DQ14

DQ10

DQ20

DQ16

DQS11_t

DQS11_c

DQ22

DQ18

DQ28

Symbol

DQ24

DQS12_t

DQS12-c

DQ30

DQ26

CB4

CB0

DQS17_t

DQS17_c

CB6

CB2

RESET_n

CKE0

ACT_n

BG0

A12

100

101

102

103

104

105

106

107

108

Symbol

CK0_t

CK0_c

EVENT_n

BA0

RAS_n/

A16

S0_n

CAS_n/

A15

ODT0

S1_n

ODT1

S2_n

DQ36

DQ32

DQS13_t

DQS13_c

DQ38

DQ34

DQ44

DQ40

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Symbol

DQS14_t

DQS14_c

DQ46

DQ42

DQ52

DQ48

DQS15_t

DQS15_c

DQ54

DQ50

DQ60

DQ56

DQS16_t

DQS16_c

DQ62

DQ58

SA0

SA1

SCL

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Symbol

REFCA

DQ5

DQ1

DQS0_c

DQS0_t

DQ7

DQ3

DQ13

DQ9

DQS1_c

DQS1_t

DQ15

DQ11

DQ21

DQ17

DQS2_c

DQS2_t

DQ23

DQ19

288-Pin DDR4 LRDIMM Back

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

Symbol

DQ29

DQ25

DQS3_c

DQS3_t

DQ31

DQ27

CB5

CB1

DQS8_c

DQS8_t

CB7

CB3

CKE1

BG1

ALERT_n

A11

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

Symbol

CK1_t

CK1_c

PARITY

BA1

A10_AP

WE_n/

A14

A13

A17

S3_n

SA2

DQ37

DQ33

DQS4_c

DQS4_t

DQ39

DQ35

DQ45

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

Symbol

DQ41

DQS5_c

DQS5_t

DQ47

DQ43

DQ53

DQ49

DQS6_c

DQS6_t

DQ55

DQ51

DQ61

DQ57

DQS7_c

DQS7_t

DQ63

DQ59

DDSPD

SDA

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4

modules. All pins listed may not be supported on this module. See Functional Block Di-

agram for pins specific to this module.

Table 5: Pin Descriptions

Symbol

Type

Input

Description

Address inputs:

Provide the row address for ACTIVATE commands and the column address for

READ/WRITE commands in order to select one location out of the memory array in the respec-

tive bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;

see individual entries in this table). The address inputs also provide the op-code during the

MODE REGISTER SET command. A17 is only defined for x4 SDRAM.

Auto precharge:

A10 is sampled during READ and WRITE commands to determine whether an

auto precharge should be performed on the accessed bank after a READ or WRITE operation

(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE com-

mand to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank

addresses.

Burst chop:

A12/BC_n is sampled during READ and WRITE commands to determine if burst

chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Com-

mand Truth Table in the DDR4 component data sheet.

Command input:

ACT_n defines the ACTIVATE command being entered along with CS_n. The

input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and

A14. See Command Truth Table.

Bank address inputs:

Define the bank (with a bank group) to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command.

Bank group address inputs:

Define the bank group to which a REFRESH, ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be

accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configura-

tions. x16-based SDRAM only has BG0.

Chip ID:

These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for

x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16

configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,

CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,

are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used

as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of

the command code.

Clock:

Differential clock inputs. All address, command, and control input signals are sampled

on the crossing of the positive edge of CK_t and the negative edge of CK_c.

Clock enable:

CKE HIGH activates and CKE LOW deactivates the internal clock signals, device

input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is

asynchronous for self refresh exit. After V

REFCA

has become stable during the power-on and ini-

tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE

must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,

CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE

and RESET_n) are disabled during self refresh.

Chip select:

All commands are masked when CS_n is registered HIGH. CS_n provides external

rank selection on systems with multiple ranks. CS_n is considered part of the command code

(CS2_n and CS3_n are not used on UDIMMs).

A10/AP

Input

A12/BC_n

Input

ACT_n

Input

BAx

Input

BGx

Input

C0, C1, C2

(RDIMM/LRDIMM on-

ly)

Input

CKx_t

CKx_c

CKEx

Input

CSx_n

Input

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM

Pin Descriptions

Table 5: Pin Descriptions (Continued)

Symbol

ODTx

Type

Input

Description

On-die termination:

ODT (registered HIGH) enables termination resistance internal to the

DDR4 SDRAM. When enabled, ODT (R

) is applied only to each DQ, DQS_t, DQS_c, DM_n/

DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is ena-

bled via the mode register). For the x16 configuration, R

is applied to each DQ, DQSU_t,

DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode

registers are programmed to disable R

Parity for command and address:

This function can be enabled or disabled via the mode

WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the

clock and at the same time as command and address with CS_n LOW.

Command inputs:

RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-

mand and/or address being entered and have multiple functions. For example, for activation

with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation com-

mand with ACT_n HIGH, these are command pins for READ, WRITE, and other commands de-

fined in Command Truth Table.

Active LOW asynchronous reset:

Reset is active when RESET_n is LOW and inactive when RE-

SET_n is HIGH. RESET_n must be HIGH during normal operation.

Serial address inputs:

Used to configure the temperature sensor/SPD EEPROM address range

on the I

C bus.

Serial clock for temperature sensor/SPD EEPROM:

Used to synchronize communication to

and from the temperature sensor/SPD EEPROM on the I

C bus.

Data input/output and check bit input/output:

Bidirectional data bus. DQ represents

DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic re-

dundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of

the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of inter-

nal V

REF

level during test via mode register setting MR[4] A[4] = HIGH; training times change

when enabled.

Input data mask and data bus inversion:

DM_n is an input mask signal for write data. Input

data is masked when DM_n is sampled LOW coincident with that input data during a write ac-

cess. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the

mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS

is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying

whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/

output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only

supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).

Serial Data:

Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS

combo device.

Data strobe:

Output with read data, input with write data. Edge-aligned with read data, cen-

tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on

DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS

corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differen-

tial data strobe only and does not support a single-ended data strobe.

Alert output:

Possesses functions such as CRC error flag and command and address parity error

flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and

returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW un-

til the on-going DRAM internal recovery transaction is complete. During connectivity test mode,

this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,

ALERT_n pin must be connected to V

on DIMMs.

Temperature event:

The EVENT_n pin is asserted by the temperature sensor when critical tem-

perature thresholds have been exceeded. This pin has no function (NF) on modules without

temperature sensors.

PARITY

Input

RAS_n/A16

CAS_n/A15

WE_n/A14

Input

RESET_n

SAx

SCL

DQx, CBx

CMOS Input

Input

I/O

DM_n/DBI_n/

TDQS_t (DMU_n,

DBIU_n), (DML_n/

DBIl_n)

I/O

SDA

DQS_t

DQS_c

DQSU_t

DQSU_c

DQSL_t

DQSL_c

ALERT_n

I/O

Output

EVENT_n

Output

09005aef863a8960

asf36c4gx72lz.pdf - Rev. D 8/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

型号	MTA36ASF4G72LZ-2G6D1	MTA36ASF4G72LZ-2G3B1
描述	MODULE DDR4 32GB LRDIMM	MODULE DDR4 SDRAM 32GB 288LRDIMM
存储器类型	DDR4 SDRAM	DDR4 SDRAM
存储容量	32GB	32GB
速度	2666MT/s	2400MT/s
封装/外壳	288-LRDIMM	288-LRDIMM