MTC-20136
ADSL Transceiver
Controller
Data Sheet
Rev. 3 - December 1998
Features
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General Description
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Dedicated controller for use
with ADSL transceiver chips
MTC-20134 and MTC-20135
Performs ADSL control func-
tions compliant with ANSI
T1.413 issue 2
- Initialization procedure
- Line monitoring during
operation
- Rate adaptive modes
Supports the modem control
interface protocol (CTRLE)
Embedded high speed ARM
microcore
Glueless connection to MTC-
20135
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Parallel or serial modem con-
trol interface (CTRLE) for glue-
less connection to manage-
ment entities
Embedded UART
Supports code download
External Bus Interface for 8
and 16-bit FEPROM and 16-bit
SDRAM
144 pins PQFP
The MTC-20136 is a dedicated con-
troller chip, specifically designed to
control operations of the Alcatel Micro-
electronics DynaMiTe chipset. The
MTC-20136 offers direct glueless inter-
faces to the MTC-20136 DMT/ATM
transciever and implements a complete
control interface for parameters and
commands exchange between trans-
ceiver and system management. All
real time ADSL-related functions (inclu-
ding EOC processing) are completely
handled by the MTC-20136.
Ordering Information
Part number
Package
Code Temp.
MTC-20136PQ-I 144 pin PQFP PQ44 -40 /+85°C
MTC-20136PQ-C 144 pin PQFP PQ44 0 /+70°C
Can also be ordered using kit number MTK-20131
Microcontroller
ARM
Microcore
ROM
RAM
MTC-20136
MTC-
20135
External Bus
Interface
SDRAM
Peripherals
TIMER
Parallel
I/O
CTRLE Data
buffer
Interface
Logic
CTRLE
UART
Local Bus
8 data
9 address
FEPROM
(optional)
RS232
General
Purpose I/Os
Control Bus
Fig. 1. MTC-20136 block diagram
MTC-20136
Functional Description
Miscellaneous
Figure 1 is showing the global block
diagram of the MTC-20136.
The functions can be grouped into the
following:
- Microcontroller
- External Bus Interface
- Control Interface (CTRLE)
- Peripherals
- Miscellaneous
This includes the clock circuitry, reset cir-
cuitry, test functions and configuration
control signals.
CTRLE
Interfaces
External Bus Interface
Microcontroller
The microcontroller block includes an
ARM-based microcore and its associat-
ed internal memory. 16 Kbytes on inter-
nal RAM and 128 x 32-bit words of
ROM are foreseen. The ROM essential-
ly contains the boot sequence needed
for code download at startup. The use
of the ROM by the microcore is defined
by the state of the TROM pin during
reset.
The external bus interface (EBI) provides
a glueless interface to 8 and 16-bit
asynchronous Flash EEPROM, 16 bit
SDRAM devices and to slave devices
with an i960-like 16 bit bus interface
with multiplexed address and data (as
available on DynaMiTe chips).
The EBI provides two chip selects
(E_nCS[1:0]) to be used for memory
access (SRAM-like), one dedicated
SDRAM chip select ((E_nCS_S) and four
chip selects (E_nCS[7:4]) to be used for
access to ADSL slave devices.
The chip selects all correspond to a
fixed 1Mbyte memory region in the
microcontroller memory map, except for
SDRAM access.
External Bus Interface
The External Bus Interface extends the
internal microcontroller bus for connec-
tion of external devices. In particular,
the bus is used to connect to the MTC-
20135 modem chip and to external
SDRAM (and optional FEEPROM).
The CTRLE functional block implements
the ADSL modem command and data
buffer and the interface logic supporting
the various physical interfaces of the
CTRLE:
- Parallel 8-bit data/ 9-bit address bus
(Intel or Motorola compatible)
- Serial bus (SPI-Like)
Peripherals
The peripherals block includes two
UARTS for RS232 interfacing to exter-
nal systems and two general purpose
parallel I/O lines.
2
MTC-20136
External pins
E_D[15:0]
E_A[19:0]
nCS[7:4]
E_CLK
ALE
nRDYRCV
nOE
nWE0
nWE1
16 bit data, multiplexed address/data
20 bit address (including commands for SDRAM)
external chip select
external clock
Address Latch Enable
Ready/Recover driven by selected device together with external pull-up
output enable
Write enable for LSB byte lane E_D[7:0]
Write enable for MSB byte lane E_D[15:8]
and logical functions is given in
Table 1
These physical pins are used for differ-
ent logical functions, depending on the
external device which is accessed.
The correspondance between physical
Table 1
Pin Name
E_A [19]
E_A [18]
E_A [17]
E_A [16]
E_A [15:0]
E_D [15:0]
E_nCS [1:0]
E_nCS [7:4]
E_nCS_S
E_Clk
E_ALE
E_nRDYRCV
E_nOE
E_nWE0
E_nWE1
MTC-20135
access function
-
-
-
-
-
AD [15:0]
-
nCS [7:4]
-
E-Clk
ALE
nRDYRCV
-
W/nR
-
SDRAM
access function
S_nRAS
S_nCAS
S_DQM0
S_DQM1
S_A [11:0]
S_Q [15:0]
-
-
S_nCS
S_Clk
-
-
-
-
S_nWE
SRAM/FEPROM
access function
E_A [19]
E_A [18]
E_A [17]
E_A [16]
E_A [15:0]
E_D [15:0]
E_nCS [1:0]
-
-
-
-
-
E_nOE
E_nWE0
E_nWE1
3
MTC-20136
Memory map modes
Three modes are defined :
a) Normal mode
The internal RAM is mapped in the
lower part of memory. This is the
normal operating mode, it allows
maximum speed access to exception
vectors.
b) Normal boot mode
If the TROM external pin is high at
reset, the MTC-20136 boots from an
external FEPROM.
c) Internal boot mode
If the TROM external pin is low at
reset, the MTC-20136 boots from its
internal ROM. This mode can be
used to perform code download from
a host.
Boot modes are used at RESET time.
MTC-20135 access
The MTC-20136 directly connects to
the MTC-20135 without glue logic.
Following features are provided for
MTC-20135 access :
- 16 bit multiplexed address/data bus
giving 64Kbyte address space per
MTC-20135.
- synchronous ready-controlled opera-
tion
- control signals : nCS[4:7], E_CLK,
ALE, W/nR, nRDYRCV
- Little endian byte ordering on 16 bit
bus
- nRDYRCV timeout mechanism
The timing diagram of the access to the
MTC-20135 is shown in figure 2:
Boot_M0 andBoot_M1 on pin 26 and 27 conrol the port to be used for down-
loading the code into the SDRAM after Bootup. This when TROM is low.
Boot_M1
(Pin27)
0
1
1
Boot_M0
(Pin26)
1
0
1
9600 Bps via serail port 1
Par. CTRL-E
Par.CTRL-E
Fig. 2. Access to MTC-20135
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MTC-20136
SDRAM
The SDRAM interface allows a glueless
interconnection of 1 SDRAM 1Mx16,
of type uPD4516161 or compatible.
Following features are provided for
SDRAM access.
- 16 bit databus and 12 bit address
bus.
- control signals : S_nCS, S_nRAS,
S_nCAS, S_nWE, S_DQM[1:0
Control signal timing
All SDRAM actions are triggered at the
rising edge of its clock.
Timing diagrams for a burst of four
16-bit accesses to 16-bit SDRAM (Fig-
ure 3 and Figure 4) show the basic
behavior of the control signals.
Fig. 3. SDRAM read access (CAS latency = 3; Burst length = 4)
Fig. 4. SDRAM write access (CAS latency = 3; Burst length = 4)
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