MTK-40130/2 0301 [1]
MTK-40130:
SH POTS chipset (GCI)
MTK-40132:
SHPOTS_µP chipset (PCM/SPI)
Short Haul Plain Old
Telephone Services
Product Brief
1. Applications
•
•
•
•
•
•
•
Voice over IP
Voice over xDSL
ISDN Terminal Adapters
µPABX
Wireless
Cable, Fibre
…
3. Features
• This compact solution
(only 3 chips, serving 2 lines)
requiring very few fixed
passive components
makes the integration in
the application easy.
• Flexibility is guaranteed by the
simple software configurability of
the system-dependent parameters
towards worldwide requirements.
• Full Software Programmability
& Control: via monitor & C/I
channel (for SHPOTS) or via
SPI-interface (for SHPOTS-µP)
• All related POTS functions:
- Caller Identity transmission
supported
- Metering Generation (internal)
- Tone generation (dual tone)
- Line State Control
(On- or Off-Hook & chipset
power management) handled
in CODSP
• BORSCHT functions:
- Battery Feeding: programmable
current limitation, power denial,
polarity reversal,…
- Overvoltage protection: by
internal over-temperature and
over-current sensing circuit
- Ringing: integrated digital
generation e.g. 5 USA REN
(programmable On/Off-time,
voltage, sine or trapezoid, …)
- Signalling supervision:
On-Hook and Off-Hook detection
(programmable detection levels
for switchhook, ring trip,
debounce times, …)
- Coding: A-or µ-law
- Hybrid 2/4 wire conversion:
transmit & receive characteristics
(Rx/Tx gains) & (real or complex)
impedance matching
- Testing: internal test switch in the
SHLIC.
2. General Description
Both chipsets can be used in all
Integrated Access Devices connecting
modern digital communication systems
to remote analog terminals (such as
telephone sets, telefax, answering
machines, modems).
The chipset comprises a CMOS
low voltage CODSP (~dual CODEC
based control device with Digital Signal
Processor) and a pair of high voltage
SHLIC (~ Short Haul Line Interface Circuit).
The CODSP processes the speech,
controls the line state and generates
ringing metering and dual tones.
The digital interface can be either
the industry standard "GCI"-interface
(MTK-40130: SHPOTS) or the
combined "PCM/SPI"-interface
(MTK-40132: SHPOTS-µP).
Each SHLIC is a line interface
buffering the speech, ringing and
metering signals, performing line
sensing and providing power to
the telephone line. It also includes
a testswitch and a 3,3V generator.
SHPOTS
GCI
CODSP
MTC-20231
or
CODSP
MTC-20233
SHLIC
MTC-30132
Protection
SHLIC
MTC-30132
MTK-40130/2
Line 0
PCM
SHPOTS_µP
SPI
Line 1
SHPOTS(_µP) chipset
5V
3.3V(*)
GND
Power Supply
BATS
BATR
(*) optional, generated by SHLIC
Block Diagram
MTK-40130/2 0301 [2]
MTK-40130/2
4. Functional Blockdiagram
CODSP
SH LIC 1
AC & DC
Loop
Control
Line
Sense
4
Control
Interface
Filters
8 Bit
compres.
Speech
DC Loop
Control
SH LIC 1 Interface
Line State
Control
TIP
RING
TEST
MTK-40130
SHPOTS: GCI
Address
GCI Bus
PCM Bus
4
GCI
or
PCM
System
Interface
The analog signal is provided on
the Rx-pin. After
amplification
of
the signal by the SHLIC, the
analog
signal
is applied to the subscriber line.
The reverse way the SHLIC senses
the line signals and sends this signal
back to the CODSP by means of the
Tx-pin.
The voice signal is handled in
the reverse way.
RINGING
Generator
Dual Tone
Generator
V3VD
+3.3V
3.3V gen
MTK-40132
SHPOTS_µP:
PCM/SPI
8 Bit
compres.
Metering
Generator
SH LIC 2
AC & DC
Loop
Control
Line
Sense
4
Control
Interface
4.3. Current Limitation (DC loop)
TIP
Filters
Speech
DC LOOP
Control
SH LIC 2 Interface
LINE STATE
CONTROL
SPI Bus
SPI
Interface
RING
RAM
ARM
ROM
TEST
PLL
3.3V gen
V3VD
+3.3V
The SHLIC senses the
DC line current
and sends it to the CODSP by means
of the DCO-pin. The CODSP will
control the DC current
to the SHLIC
via the DCC-pin in case the current
limitation level is reached, thus
protecting the chipset against DC
overcurrent situations.
Via the
line state control
block in
the CODSP, the SHLIC state (power
denial, power down, power up [for
offhook, ADSI, active ringing], reset)
is controlled by means of 4 pins.
VDD BATS BATR
+5V -24V -60V
4.1 The digital Interface
PCM/SPI-interface
• The Pulse Code Modulation is a
standardized interface transporting
the speech. The clock frequency can
be between 512, and 8196 kHz in
steps of 512 kHz. It can address up
to 64 CODSP-chipsets, representing
up to 128 analog interfaces.
• The Serial Programming Interface
is the microprocessor interface for
configuration and control. It is a
serial bus with a dynamically
changeable clock frequency,
independent of the PCM clock.
The control is simplified by an 8-bit
control word activating the
commonly used fuctions, while
the line state can be monitored
via dedicated pins.
GCI-interface
• The General Circuit Interface (an
interface specification, developed
jointly by Alcatel, Italtel, GPT and
Siemens) is a standardized interface,
transporting the speech (B1/B2-
channel), the programming signals
(Monitoring channel) and the
Signalling (C/I channel). The clock
frequency can be 512, 1536, 2048,
4096 kHz. Using only 4 wires it
can address up to 8 CODSP-chipsets,
representing up to 16 analog
interfaces.
4.4. Other Functional Blocks
The CODSP has following additional
blocks: the
digital ringing signal-,
the metering pulses
(12kHz or 16kHz)
and the dual tonegeneration.
The tone-
generation per channel comprises the
sum of two programmable sine-wave
frequencies and amplitudes. In this
way the most common call-progress
and information tones, melody notes
or DTMF tones can be generated.
Both the metering- and tone signals
can be mixed with the voice signal.
Also the caller identity can be
transmitted through the speech
channels during On-Hook condition.
Furthermore the SHLIC has a
switch
for the line test purposes and the
3,3V generation
for the CODSP.
4.2. Speech handling (AC loop)
The CODSP handles the speech
data for both lines. This includes
the
decompression
of the incoming
digital signal from 8-bit A- or
µ-law (G.711) into linear code,
the
filtering
according ITU-T (G.712)
and the
digital/analog
conversion.
2
MTK-40130/2 0301 [3]
MTK-40130/2
5. Electrical characteristics
5.1. Absolute maximum ratings
Parameter
BATR
BATS
DBAT
VDDA
GNDB
Description
ringing battery voltage (ref to GNDB)
speech battery voltage (ref to GNDB)
difference voltage (= BATR-BATS)
supply voltage (ref. To GNDA)
(ref. To GNDA)
voltage on any low voltage pins (ref. To GND*)
ambient temperature under bias of SHLIC
maximum absolute power dissipation with Tamb=85°C
V3VA, V3VD supply voltage to CODSP
voltage on any device pin except 5V tolerant pins
voltage on 5V tolerant pins
function temperature under bias of CODSP
Min.
-75
-35
-40
-0,5
-0,5
-0,5
-40
VSS-0,3
VSS-0,3
VSS-0,3
-55
Max.
+0,5
+0,5
+0,5
+7
+0,5
V3V+0,5
+85
1,3
4
V3V+0,3
+5,5
+150
Unit
V
V
V
V
V
V
°C
W
V
V
V
°C
SHLIC
CODSP
V3V
Vin
Vin
5.2. Operating ranges
Parameter
BATR
BATS
DBAT
VDDA
V3V
Tamb (I)
Tamb (C)
Description
ringing battery voltage (ref to GNDB)
speech battery voltage (ref to GNDB)
difference voltage (= BATR-BATS)
supply voltage (ref. To GNDA)
V3VA, V3VD supply voltage to CODSP (~3,3+/- 8%)
ambient temperature for industrial range
ambient temperature for commercial range
Min.
-72
-35
-40
+4,75
+3,036
-40
0
Typ.
-65
-32
-33
+5
+3,3
Max.
-18
-18
0
+5,5
+3,564
+85
+70
Unit
V
V
V
V
V
°C
°C
SHLIC
CODSP
chipset
5.3. Current Consumption
(1)
Phase
non-active
SHLIC
Condition
ON HOOK
Power Denial
Active Ringing (2)
Silent Ringing
ADSI
OFF HOOK (2)
Programmed
BAT selection
BATS
BATR
BATS
BATR
BATS
BATR
BATS
BATR
BATS
VDD
TYP
2,80
2,80
2,80
6,00
2,80
2,80
4,30
4,30
4,30
Max
4,00
4,00
4,00
8,00
4,00
4,00
5,50
5,50
5,50
BATS
TYP
Max
0,90
2,50
0,08
0,15
0,37
1,00
1,15
2,00
0,90
2,50
0,08
0,15
1,98
2,90
0,08
0,15
2,15
2,90
BATR
TYP
Max
0,05
0,32
1,40
2,30
0,10
0,60
3,40
5,00
0,05
0,32
1,40
2,30
0,05
0,32
2,50
5,00
0,05
0,32
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
active
3
MTK-40130/2 0301 [4]
MTK-40130/2
Condition
(per SHLIC phase)
Both SHLIC are non-active
One SHLIC is active
One SHLIC is active (3)
Both SHLIC are active
V3VA + V3VD
TYP
Max
6,8
8,7
44,4
52,0
35,1
41,0
47,7
52,0
Unit
mA
mA
mA
mA
(1) Typical values are at typical operating conditions and VDD = 5V; BATS = -24V; BATR = -48V; V3VD = V3VA = 3,3V
Maximum values are at maximum operating voltages (absolute value) except V3VA = V3VD = 3,45V
(2) Current due to the load is not included and has to be calculated separately based on line load specification
(3) After programming the sleep-mode
5.4. Key programmable parameters
DC feed
DC loop current limit
DC loop off-hook detect level
Line polarity, power down, power denial
Central Office Impedance (Zco), real
Central Office Impedance, Rs
Central Office Impedance, Rp
Central Office Impedance, Cp
Transmit gain
Receive gain
RX and TX filter
metering amplitude
metering frequency
ringing amplitude (50Hz sine)
ringing amplitude (20Hz sine)
ringing frequency
ringing distortion (sine wave)
ringing distortion (trapezoid)
ringing cadence
ring-trip detect level, DC
ring-trip detect level, AC
20 to 70*
10
/
600 to 900
160 to 500
300 to 1k
31 to 740
-6 to +1
-12 to +1
/
>200
12 or 16
>40
>40
16,66 - 20 - 25 - 50
<5
<10
/
10
/
mA (*: provided Pmax is respected)
mA nominal (2mA hysteresis)
selectable per channel
Ohm
Ohm equivalent
Ohm equivalent
nF equivalent
dBr (in 0,25dB steps)
dBr (in 0,25dB steps)
ITU-T G.712 programmable
mVrms over 200 Ohm load
(on condition Rline= 130 Ohm)
kHz
Vrms, 4x REN (=2kOhm + 1µF)
Vrms, 5x USA REN (=6,8kOhm + 8µF)
Hz
%
%
program controlled or automatic
mA (silent ringing phase)
mA (active ringing phase)
6. Ordering Information
Chipset
MTK-40130-C
MTK-40130-I
MTK-40132-C
MTK-40132-I
Description
1x MTC-20231-PQ-C
2x MTC-30132-SO-C
1x MTC-20231-PQ-I
2x MTC-30132-SO-I
1x MTC-20233-PQ-C
2x MTC-30132-SO-C
1x MTC-20233-PQ-I
2x MTC-30132-SO-I
Name
CODSP
SHLIC
CODSP
SHLIC
CODSP
SHLIC
CODSP
SHLIC
Version
GCI
GCI
PCM/SPI
PCM/SPI
Package
44 pinPQFP PQ44
28 pinSO SO28
44 pinPQFP PQ44
28 pinSO SO28
44 pinPQFP PQ44
28 pinSO SO28
44 pinPQFP PQ44
28 pinSO SO28
Temp
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
CODSP
AC speech
Metering
Ringing
4
MTK-40130/2 0301 [5]
MTK-40130/2
7. Typical Application Schematic
Fig.a: For MTK-40130: SHPOTS (GCI-version)
V3VD
User
Ouputs
(examples)
SPIDI
SPIDO
SPICS
SPICK
V3VD - 5V
Rpu
DU
DD
FSC
DCL
0,1
0,1
0,1
0,1
GCIM
AD0
AD1
AD2
DET0~
DET1~
V3VD ~ 5V
Fig.b: For MTK-40132: SHPOTS_µP (PCM/SPI-version)
V3VD
OR
PCM
Port
Rpu
PCMIN
PCMOUT
FRAME
PCMCLK
V3VD ~ 5V
Rpu
Rpu
SPIIN
SPIOUT
SPICLK
CH0~
CH1~
GCI
Port
GCI mode
and
timeslot
address
SPI
Port
V3VD
User
Ouputs
(examples)
SPIDI
SPIDO
SPICS
SPICK
V3VD
TST[0]
BR[0]
RNG[0]
PU[0]
RX[0]
TX[0]
DCC[0]
DCO[0]
V3V
SA
AW
1nF
SSB
SB
BW
SHLIC
MTC-30132
1nF
BAT
BATS
BATR
VDD
VAG
100nF
VAG
GNDA
DCLF2
GNDB
DCLF1
10kΩ
CODSP
MTC-20231/MTC-20233
V3VD
VAG
Dpwrs
1kΩ
100nF
-
0
0
0
1
0
0
0
0
PWRS
JTDO
JTDI
JTCK
JTMS
JTRS
PLLCK
TEST
ZOUT
SCLK
GNDA
GNDD
TST[1]
BR[1]
RNG[1]
PU[1]
RX[1]
TX[1]
DCC[1]
DCO[1]
V3VA
10µF+100nF
TST
BR
RNG
PU
RX
TX
DCC
DCO
DCI
CPLL
4,7nF
GNDA
DCLF2
V3V
SSB
SB
BW
SHLIC
MTC-30132
1nF
BAT
BATS
Dp
BATR
VDD
GNDB
DCLF1
10kΩ
10kΩ
470nF
470nF
VddA
Cp
SA
AW
1nF
510Ω
RB2
H
Rprot
protection
Vbats
Vbatr
LINE 1
10kΩ
470nF
50Ω
470nF
Rprot
510Ω
50Ω
H
Rprot
protection
Vbats
Dpd
Vbatr
VddA
LINE 0
Fig.a
completes
MTC-20231
V3VD - 5V
10µF+100nF
50Ω
Rprot
a
or
Rpu
TST
BR
RNG
PU
RX
TX
DCC
DCO
DCI
b
GCI
Port
Fig.b
completes
MTC-20233
0,1
0,1
0,1
0,1
DU
DD
FSC
DCL
GCIM
AD0
AD1
AD2
100nF
100nF
100nF
330nF
Dp
Cp
GCI mode
and
timeslot
address
a
b
Device test
JTAG
address
Device
test
330nF
5
