MYSON
TECHNOLOGY
FEATURES
•
•
•
•
•
MTV003N
(MTV003)
Microprocessor Compatible Monitor Controller
Synchronous signal processing for use in green monitor applications.
Easy command interface for external microprocessor controls.
D/A converters up to 12V output.
Built-in self-test pattern generator.
On-chip clock oscillator allows external TTL level clock signal input.
GENERAL DESCRIPTION
MTV003 is intended for use in digital-controlled, power-conscious (Green) monitor applications. It integrates 4
major function blocks traditionally implemented in discrete parts and provides an easy interface for
microprocessor controls. The functional blocks included in MTV003 are: SYNC processing, D/A converters,
self-test pattern generator and command interface.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV003 Revision 2.3 07/01/1998
1/13
MYSON
TECHNOLOGY
1.0 CONNECTION DIAGRAM
(20 PIN PDIP 300 MIL PACKAGE)
MTV003N
(MTV003)
2.0 PIN DESCRIPTIONS
Name
VSS
DA0
I/O
O
Pin#
1
2
Function
Ground
(0 V).
Open-Drain PWM
(Pulse Width Modulation)
D/A Converter 0.
The
output pulse width is programmable by writing data to
Reg10
with
8-bit resolution to control the pulse width duration from 0 to 255/256.
The output frequency is 31.25KHz (or15.625KHz). In applications, the
external pull-up resistor can be connected to 12V for the desired full-
scale output.
Open-Drain PWM D/A Converter 1. See DA0.
The output pulse
width is programmable by
Reg11.
Open-Drain PWM D/A Converter 2. See DA0.
The output pulse
width is programmable by
Reg12.
Horizontal Blank.
The pulse width and the delay of HBLANK vs.HS
input leading edges are programmable by
Reg7 and Reg6,
respectively.
Vertical Blank.
The output pulse width is programmable by
Reg9.
Crystal 1.
Used to interface to the oscillator. An 8MHz(or 4MHz)
crystal must be connected between this pin and pin X2. An appropriate
capacitor to Ground, whose value depends on the specified CLof the
crystal, must be connected. This pin can also be used as a direct input
when the external oscillator is used.
MTV003 Revision 2.3 07/01/1998
2/13
DA1
DA2
HBLANK
O
O
O
3
4
5
VBLANK
X1
O
I/O
6
7
MYSON
TECHNOLOGY
Name
X2
I/O
O
Pin#
8
MTV003N
(MTV003)
HS
I
9
VS
I
10
CMDB
I
11
DCK
I
12
DIO
I/O
13
STOUT
O
14
XDA4
XDA3
XDA2
XDA1
XDA0
VDD
O
O
O
O
O
15
16
17
18
19
20
Function
Crystal 2. See X1.
An appropriate capacitor to Ground, whose value
depends on the specified CLof the crystal, must be connected. For the
external clock source, this pin must be tied to Ground.
Horizontal Sync.
Horizontal synchronous signal input. The input level
is TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm
pull-up resistor is connected to this pin.
Vertical Sync.
Vertical synchronous signal input. The input level is
TTL compatible with internal 0.2V hysteresis. An internal 50K Ohm
pull-up resistor is connected to this pin.
Command Interface Enabler.
A low active pin which must be forced
to low in excess of 16 cycles of DCK for 1 successful access of
command interface. It has an internal 50K Ohm pull-up resistor.
Command Interface Clock.
This pin is used as the timing base for
command interface. The address or data portion for the serial in (out)
of DIO is recognized by counting the number of DCKs. It has an
internal 50K Ohm pull-up resistor.
Command Interface Data.
This pin is a bidirectional pin. A
microprocessor can access any internal command registers through
the protocol of the address portion followed by the succeeding data
portion. It must complete 16 full DCK cycles for a valid access.
Self-Test Video Output.
(for self-test mode) This pin is the
video
output pin of the self-test pattern generator. The generator enabler,
pattern modes, output band selection and output enabler are
programmed by
Reg16.
CMOS PWM D/A Converter 4. See DA0.
The output pulse width can
be programmed by
Reg30.
It is a CMOS type output.
CMOS PWM D/A Converter 3. See DA0.
The output pulse width can
be programmed by
Reg29.
It is a CMOS type output.
CMOS PWM D/A Converter 2. See DA0.
The output pulse width can
be programmed by
Reg28.
It is a CMOS type output.
CMOS PWM D/A Converter 1. See DA0.
The output pulse width can
be programmed by
Reg27.
It is a CMOS type output.
CMOS PWM D/A Converter 0. See DA0.
The output pulse width can
be programmed by
Reg26.
It is a CMOS type output.
Positive Power Supply.
+5 volts. 2 decoupling capacitors, 0.1 uF and
100 uF, must be connected to VDD and Ground as close to the device
as possible.
3.0 FUNCTIONAL DESCRIPTION
3.1 Crystal Oscillator and Clock Generator
The crystal oscillator shall be connected to an 8MHz(or 4MHz) crystal. X1, as shown in Fig.1, can be used as
an input source for the external clock or an output clock source to drive the external MCU. All timing
specifications are based on the frequency of X1 (or X1 divided by 2).
3.2 PWM D/A Converter
There are 2 types of D/A converters with 8-bit resolution: open-drain type (DA0 to DA2) and CMOS type (XDA0
to XDA4). The sampling frequency is 31.25KHz or 15.625KHz, depending on the use of the crystal. The
maximum external voltage applied is 12V for the open-drain type, and the output pulse width is programmable
MTV003 Revision 2.3 07/01/1998
3/13
MYSON
TECHNOLOGY
for each converter by setting the corresponding register.
3.3 SYNC Processor
MTV003N
(MTV003)
The sync processor contains the following functions: polarity detection, presence detection, H-Freq counter,
V-Freq counter and sync signal separation for input SYNC sources (HS and VS). It can be programmed to
change the detected polarity status and output polarity of SYNC pins (HBLANK and VBLANK) by using the
command interface. The timing diagrams of sync processing are shown as Fig. 2 in section 8.0. The internal
SYNC signals (Hsync and Vsync) are extracted from different sources according to the following modes of
operation.
Mode
Separate(H+V)
Composite(H/V)
Suspend
Off
VS
present
not present
present
not present
HS
present
present
not present
not present
Comment
HS = H or H/V sync
HS= H/V sync
-
-
1
2
3
4
3.4 H-Freq Table
After the "start H-Freq count" command is issued over 10 ms (for 15.7KHz) and HCFF(H-Freq Count Finished
Flag) is set
High,
the H-Freq output (HF9 - HF0) is valid. The output value of H-Freq is calculated using the
following formula:
output value = [(1/fHfreq(KHz)) x 64 x 4000] / 16
H-Freq(KHz)
15.7
18.7
21.8
30
31.5
33.5
35.5
36.8
38
40
48
50
57
60
64
100
Output value hexadecimal 11 bits decimal
3FB
1019
357
855
2DD
733
215
533
1FB
507
1DD
477
1C2
450
1B2
434
1A5
421
190
400
14D
333
140
320
118
280
10A
266
0FA
250
0A0
160
Tolerance (%)
0.0981354
0.1169591
0.1364256
0.1876172
0.1972386
0.2096436
0.2222222
0.2304147
0.2375297
0.2500000
0.3003003
0.3125000
0.3571428
0.3759398
0.4000000
0.6250000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3.5 V-Freq Table
After the "start V-Freq count" command is issued over 120 ms (for 50HZ) and VCFF (V-Freq Count Finish Flag)
is set
High,
the V-Freq output (VF8 - VF0) is valid. The output value of V-Freq is calculated according to the
following formula:
output value = [(4/fVfreq(Hz)) x 4000000] / (64 x 16)
MTV003 Revision 2.3 07/01/1998
4/13
MYSON
TECHNOLOGY
V-Freq(Hz)
1
2
3
4
5
6
7
8
9
10
11
12
13
20
56.25
59.94
60
60.32
60.53
66.67
70.069
70.08
72
72.378
72.7
87
Output value hexadecimal 9 bits decimal
30D
781
115
277
104
260
104
260
103
259
102
258
0EA
234
0DE
222
0DE
222
0D9
217
0D7
215
0D6
214
0B3
179
MTV003N
(MTV003)
Tolerance (%)
0.12804
0.36101
0.38461
0.38461
0.38610
0.38759
0.42735
0.45045
0.45045
0.46082
0.46511
0.46728
0.55865
3.6 Command Interface
The command interface contains 3 pins. Each transfer of command is comprised of 16 DCK clock periods. The
first 8 DCK clocks are for the address and direction of DIO, and the succeeding 8 DCK clocks are for the data.
Each transfer is initiated by setting CMDB
Low.
The CMDB pin must be pulled
High
after data transfer is
completed.
- Command Format
B0 - 4 (ADD4
- 0)
B5
(W/RB)
B6 - 7
B8 - 15 (
DA0 - 7
)
(
DA7 - 0
)
- Register Allocation
a. Read Transfer
Address Portion
ADD4-0
W/RB
B0 - 4
B5
00000
0
00001
0
00010
0
00011
0
00100
0
Data Portion
DA7 - 0
B11
B12
VSpre
x
HF4
x
VF4
HVpre
HCFF
HF3
x
VF3
: Address of the registers.
: Transfer direction, 1=write, 0=read.
: Reserved.
: Data input when
W/RB=1.
Data output when
W/RB=0.
Reg #
Reg0
Reg1
Reg2
Reg3
Reg4
B8
Hpol
x
HF7
x
VF7
B9
Vpol
x
HF6
x
VF6
B10
HSpre
x
HF5
x
VF5
B13
Hsl
HF10
HF2
x
VF2
B14
Vsl
HF9
HF1
VCFF
VF1
B15
x
HF8
HF0
VF8
VF0
Table 4
b. Write Transfer
Address Portion
ADD4-0
W/RB
B0 - 4
B5
00000
1
00001
1
00010
1
00011
1
Data Portion
DA0 - 7
B11
B12
x
Hpf1
x
x
x
VBpl
x
x
Reg #
Reg0
Reg1
Reg2
Reg3
B8
x
Vpf0
x
CLK4M
B9
x
Vpf1
x
TEST
B10
x
Hpf0
x
x
B13
x
HBpl
x
x
B14
x
HVcvs
x
x
B15
x
x
x
x
MTV003 Revision 2.3 07/01/1998
5/13
