Advance Information
LANCAM
®
WL Family
APPLICATION BENEFITS
Enhances Ethernet and Token-Ring LAN bridges
and switches:
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64-bit width stores 48-bit MAC address plus
associated data (Port ID, time stamp,
“permanent” flag)
32-bit I/O supports ports of fast (100 Mb)
Ethernet or Gigabit Ethernet
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Station list depth flexibility with choice
of pin-compatible device densities and
glue-free cascading
3.3 Volt supply for low power operation
Industrial temperature grades for harsh
environments
DISTINCTIVE CHARACTERISTICS
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32,768 (MU9C7485) and 16,384 (MU9C6485) word
CMOS content-addressable memories (CAMs)
64-bit word width
32-bit I/O
Fast 50 ns compare speed
Dual configuration register set for rapid context
switching
Increased flexibility of MUSIC’s patented CAM/RAM
partitioning
160-Pin in PQFP package
3.3 Volt operation
IEEE 1149.1 (JTAG) compliant
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(3 2 )
M UX
D A TA (6 4 )
I/ O
BU FFE R S
DQ 3 1 – 0
(3 2 )
(3 2 )
TR A N S LA TE
(8 02 .3 /8 0 2 .5 )
DE M U X
D A TA (6 4 )
(3 2 )
S O URCE AND
D E S TIN A TIO N
S E G M E NT
C O U N TE R S
CO M P ARAND
M A S K R E G IS TE R 1
M A S K R E G IS TE R 2
C O MM A N D S
& S TA TU S
3 2 K or 1 6 K X 2 V A L ID ITY B ITS
A D D R E S S D E CO D E R
P R IO R ITY E N C O D E R
/W
/E
/CM
/EC
/R E S E T
17/ 16
/M A
/M M
2
CO NT RO L
LO G I C
CO NT RO L
AND S T AT US
RE G IS T ER S
CAM A RR AY
3 2 K or 1 6 K
W O RD S
X 6 4 B ITS
15/ 14
/ FF
F LA G
L O G IC
/ FI
/M F
/M I
Block Diagram
LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is
a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
1 October 1998 Rev. 0a
LANCAM WL Family
GENERAL DESCRIPTION
The MU9C7485 and MU9C6485 LANCAM WLs are 64-bit
wide content-addressable memories (CAMs), featuring a 32-
bit wide interface. This interface doubles the available I/O
bandwidth in many applications while maintaining the same
powerful enhanced architecture and instruction set as the
MU9C2480A/L.
Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In a RAM, the input to the device is an
address and the output is the data stored at that address. In a
CAM, the input is a data sample and the output is a flag to
indicate a match and the address of the matching data. As a
result, a CAM searches large databases for matching data in a
short, constant time period, no matter how many entries are in
the database. The ability to search data words up to 64 bits
wide allows large address spaces to be searched rapidly and
efficiently. A patented architecture links each CAM entry to
associated data and makes this data available for use after a
successful compare operation.
While the LANCAM WLs are optimized for LAN network
address filtering, they are also well suited for applications that
require high-speed data searching, such as virtual memories
and cache management, data compression and encryption,
database accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM WL, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether or
not one or more of the valid CAM locations contains data
that match the target data. The status of each CAM location
is determined by two validity bits at each memory location.
The two bits are encoded to render four validity conditions:
Valid, Empty, Skip, and RAM, as shown in Table 1. The memory
can be partitioned into CAM and associated RAM segments
on 16-bit boundaries, but by using one of the two available
mask registers, the CAM/RAM partitioning can be set at any
arbitrary size between zero and 64 bits.
The LANCAM WL’s internal data path is 64 bits wide for
rapid internal comparison and data movement. A data
translation facility converts between IEEE 802.3 (CSMA/CD
“Ethernet”) and 802.5 (Token Ring) address formats. Vertical
cascading of additional LANCAM WLs in a daisy chain
fashion extends the CAM memory depth for large databases.
Cascading requires no external logic. Loading data to the
Control, Comparand, and mask registers automatically triggers
a compare. Compares may also be initiated by a command to
the device. Associated RAM data is available immediately
after a successful compare operation. The Status register reports
the results of compares including all flags and addresses. Two
mask registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The random
access validity type allows additional masks to be stored in
the CAM array where they may be retrieved rapidly.
A simple four-wire control interface and commands loaded
into the Instruction decoder control the device. A powerful
instruction set increases the control flexibility and minimizes
software overhead. Additionally, dedicated pins for match and
multiple-match flags enhance performance when the device is
controlled by a state machine. These and other features make
the LANCAM WL a powerful associative memory that
drastically reduces search delays.
Skip Bit
0
0
1
1
Empty Bit
0
1
0
1
Entry Type
Valid
Empty
Skip
RAM
/W
LOW
LOW
HIGH
HIGH
Table 1: Entry Types vs. Validity Bits
/CM
Cycle Type
LOW
Command Write Cycle
Data Write Cycle
HIGH
LOW
Command Read Cycle
HIGH
Data Read Cycle
Table 2: I/O Cycles
Rev. 0a
2
LANCAM WL Family
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, /EC. The rising
edge locks the daisy chain, turns off the DQ pins, and
clocks the Destination and Source Segment counters. The
four cycle types enabled by /E are shown in Table 2.
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ31–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a comparison,
as shown in Figure 6 on page 15. If /EC is LOW at the
falling edge of /E in a given cycle, the /MF output is enabled.
Otherwise, the /MF output is held HIGH. The /EC signal
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VCC
VCC
NC
NC
GND
GND
NC
NC
NC
NC
VCC
VCC
NC
NC
GND
G ND
NC
NC
NC
NC
VCC
VCC
NC
NC
NC
NC
GND
GND
/EC
/C M
NC
NC
VCC
VCC
NC
NC
/MA
/F I
GND
GND
GND
DQ0
DQ1
VCC
VCC
DQ2
DQ3
G ND
GND
DQ4
DQ5
VCC
VCC
DQ6
DQ7
GND
GND
DQ8
DQ9
VCC
VCC
D Q 10
D Q 11
G ND
G ND
D Q 12
D Q 13
VCC
VCC
D Q 14
D Q 15
GND
GND
D Q 16
D Q 17
VCC
VCC
D Q 18
D Q 19
GND
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
160-Pin PQFP
(Top View)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VCC
NC
NC
GND
GND
NC
NC
/FF
/M I
VCC
/MF
/M M
GND
GND
/R ESET
VCC
VCC
/E
/W
NC
NC
VCC
GND
GND
NC
NC
NC
NC
VCC
VCC
/T RST
T CLK
T MS
T DI
GND
GND
T DO
NC
NC
VCC
VCC
D Q 20
D Q 21
GND
GND
D Q 22
D Q 23
VCC
VCC
D Q 24
D Q 25
G ND
G ND
D Q 26
D Q 27
VCC
VCC
D Q 28
D Q 29
G ND
G ND
D Q 30
D Q 31
VCC
VCC
NC
NC
G ND
G ND
NC
NC
NC
NC
VCC
VCC
NC
NC
NC
NC
G ND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pinout Diagram
3
Rev. 0a
LANCAM WL Family
PIN DESCRIPTIONS
Continued
also enables the /MF–/MI daisy chain, which serves to
select the device with the highest-priority match in a string
of LANCAMs. Tables 6a and 6b on page 12 explain the
effect of the /EC signal on a device with or without a match
in both Standard and Enhanced modes. /EC must be HIGH
during initialization.
DQ31–0 (Data Bus, I/O, TTL)
The DQ31–0 lines convey data, commands, and status
to and from the LANCAM WL, as shown in Table 3. /W
and /CM control the direction and nature of the
information that flows to or from the device. When /E is
HIGH, DQ31–0 go to HIGH-Z.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on
the first cycle that /EC is registered LOW by the previous
falling edge of /E; see Figure 6 on page 15). In a daisy
chain, valid match(es) in higher priority devices are passed
from the /MI input to /MF. If the daisy chain is enabled but
the match flag is disabled in the Control register, the /MF
output only depends on the /MI input of the device (/MF=/
MI). /MF is HIGH if there is no match or when the daisy
chain is disabled (/E goes HIGH when /EC was HIGH on the
previous falling edge of /E). The System Match flag is the
/MF pin of the last device in the daisy chain. /MF will be
reset when the active configuration register set is changed.
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in
the chain must be tied HIGH.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare
cycle. The /MA output is not qualified by /EC or /MI,
and reflects the match flag from that specific device’s
Status register. /MA will be reset when the active register
set is changed.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid
match occurs during the current or the last previous
compare cycle. The /MM output is not qualified by /EC
or /MI, and reflects the multiple match flag from that
specific device’s Status register. /MM will be reset when
the active register set is changed.
Rev. 0a
4
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device (and
in the daisy chain above the device as indicated by the /FI
pin). The System Full flag is the /FF pin of the last device in the
daisy chain, and the Next Free address resides in the device
with /FI LOW and /FF HIGH. If disabled in the Control register,
the /FF output only depends on the /FI input (/FF = /FI).
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected
to the /FF output of the previous device in the daisy chain.
The /FI pin on the first device in a chain must be tied LOW.
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 5 on page 10. The /RESET pin
should be driven by TTL levels, not directly by an RC
timeout. /E must be kept HIGH during /RESET.
/TRST (JTAG Reset, Input, TTL)
The /TRST input is the Test Reset input. It is internally
pulled HIGH with a 25K resistor (minimum). This input must
be tied to /RESET if in use or tied LOW when not in use.
/TCLK (JTAG Test Clock, Input, TTL)
The /TCLK input is the Test Clock input. It must be
connected to a valid logic level when not in use.
TMS (JTAG Test mode Select, Input, TTL)
The TMS input is the Test Mode Select input. It is internally
pulled HIGH with a 25K resistor (minimum).
TDI (JTAG Test Data Input, Input, TTL)
The TDI input is the Test Data input. It is internally pulled
HIGH with a 25K resistor (minimum).
TDO (JTAG Test Data Output, Ouput, TTL)
The TDO output is the Test Data output.
VCC, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the LANCAM
WL. VCC must meet the voltage supply requirements in the
Operating Conditions section relative to the GND pins, which
are at 0 Volts (system reference potential), for correct operation
of the device. All the ground and power pins must be
connected to their respective planes with adequate bulk and
high frequency bypassing capacitors in close proximity to
the device.
LANCAM WL Family
FUNCTIONAL DESCRIPTION
The LANCAM WL is a content-addressable memory
(CAM) with 32-bit I/O for network address filtering,
virtual memory, data compression, caching, and table
lookup applications. The memory consists of static
CAM, organized in 64-bit data fields. Each data field can
be partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a
compare. During automatic comparison cycles, data in
the Comparand register is automatically compared with
the “Valid” entries in the memory array. The Device ID can be
read using a TCO PS instruction (see Table 14 on page 24).
The data inputs and outputs of the LANCAM WL are
multiplexed for data and instructions over a 32-bit
I/O bus. Internally, data is handled on a 64-bit basis,
since the Comparand register, the mask registers, and
each memory entry are 64 bits wide. Memory entries are
globally configurable into CAM and RAM segments on
16-bit boundaries, as described in US Patent 5,383,146
assigned to MUSIC Semiconductors. Seven different
CAM/RAM splits are possible, with the CAM width
going from one to four segments, and the remaining RAM
width going from three to zero segments. Finer resolution
on compare width is possible by invoking a mask register
during a compare, which does global masking on a bit
basis. The CAM subfield contains the associative data,
which enters into compares, while the RAM subfield
contains the associated data, which is not compared. In
LAN bridges, the RAM subfield can hold, for example,
port-address and aging information related to the
destination or source address information held in the
CAM subfield of a given location. In a translation
application, the CAM field can hold the dictionary
entries, while the RAM field holds the translations, with
almost instantaneous response.
Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
Empty, Valid, Skip, or RAM. When data is written to the
active Comparand register, and the active Segment
Control register reaches its terminal count, the contents
of the Comparand register are automatically compared
with the CAM portion of all the valid entries in the
memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a
time. A Compare instruction can then be used to force
another compare between the Comparand register and
the CAM portion of memory entries of any one of the
four validity types. After a Read or Move from Memory
operation, the validity bits of the location read or moved
will be copied into the Status register, where they can be
read from the Status register using Command Read cycles.
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match
or Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also
be written directly to the memory from the DQ bus using
any of the above addressing modes. The Address
register may be directly loaded and may be set to
increment or decrement, allowing DMA-type reading or
writing from memory.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
/W
LOW
/CM
LOW
Cycle Type
Command write
HIGH
LOW
HIGH
Notes:
LOW
HIGH
HIGH
Command read
TCO 2nd cycle
Data write
Data read
“f” Bit
0
1
0
1
X
X
X
X
DQ31–16
Non-TCO Instruction
Non-TCO Instruction
TCO Instruction (Read register)*
TCO Instruction (Write register)
Status Register bits 31–16
Status Register bits 31–16†
Data to CR, MRX, Mem.
Data from CR, MRX, Mem.
DQ15–0
XXXX
Absolute Address
XXXX
Value to Register
Status Register bits 15–0
Register contents*
Data to CR, MRX, Mem.
Data from CR, MRX, Mem.
*
A CW of a TCO Instruction with the “f” bit set to 0 sets up a Register read in the following cycle. The following
cycle must be a Command Read cycle, otherwise the register read will be cancelled.
†
Upper 16 bits will be Status Register bits 31–16, except for a read of the Page Address register, in which case
they will be all zeros.
Table 3: DQ Bus Multiplexing
5
Rev. 0a
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