PRELIMINARY
MX10E8050I /
MX10E8050IA
Major Difference
Feature
Product
Default
Clock mode
ISP
IAP
Package
MX10E8050IPC
MX10E8050IQC
MX10E8050IUC
6
6
UART
YES
44 Pin PDIP
44 Pin PLCC
44 Pin LQFP
MX10E8050IAQC
I
2
C
YES
44 Pin PLCC
P/N:PM0887
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.6, MAR. 28, 2005
1
PRELIMINARY
MX10E8050I /
MX10E8050IA
FEATURES
- 80C51 CPU core
- 3.0 ~ 3.6V voltage range
- On-chip Flash program memory with in-system
programming ( ISP )
- Operating frequency up to 40MHz (12x), 20MHz(6x)
- 64K bytes Flash memory for code memory
- 1280 bytes internal data RAM
- Low power consumption
- Code and data memory expandable to 64K Bytes
- Four 8 bit and one 4 bit general purpose I/O ports
- Three standard 16-bit Timers
- In - Application Programming( IAP ) capability
- On-chip Watch Dog Timer
- Four channel PWM outputs/4bit general purpose I/O
ports ( PLCC & LQFP only )
- UART
- 7 interrupt sources with four priority level
- 5 volt tolerant input
- 400kb/s I
2
C
- 6x / 12x clock mode
PIN Configurations
6
1
40
7
39
PLCC44
17
29
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P4.2/PWM2
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
P4.3/PWM3
P3.1/TxD
P3.2/INT0
P3.3/INT1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
P4.0/PWM0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
28
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.7/A15
PSEN
ALE
P4.1/PWM1
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
P/N:PM0887
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.6, MAR. 28, 2005
2
PRELIMINARY
MX10E8050I /
MX10E8050IA
44
34
1
33
LQFP44
11
23
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
P4.3/PWM3
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
V
SS
P4.0/PWM0
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
P4.1/PWM1
EA
P0.7/AD7
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
P4.2/PWM2
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
Table. 1 Pin Description
Package Type
SYMBOL
P0.0-P0.7
P2.0-P2.7
P1.0-P1.7
P3.0-P3.7
P4.0~P4.3/
RESET
VCC
VSS
XTAL1
XTAL2
PSEN
ALE
EA
PDIP PLCC
PIN
PIN
39-32 43-36
21-28 24-31
1-8
2-9
10-17
NA
9
40
20
19
18
29
30
31
11,13-19
23,34,1,12
10
44
22
21
20
32
33
35
LQFP
PIN
37-30
18-25
40-44,1-3
5,7-13
17,28,39,6
4
38
16
15
14
26
27
29
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
O
O
O
I
DESCRIPTION
Port:8-bit open drain bidirectional I/O Port
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up
, except P1.6 and P1.7
Port: 8-bit quasi-bidirectional I/O Port with internal pull-up
4bit Quasi-bidirectional I/O port or PWM PWM0~PWM3
reset input
Positive power supply
Ground
XTAL connection input
XTAL connection output
Program store enable output
Address latch enable output
External access input
P/N:PM0887
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.6, MAR. 28, 2005
3
PDIP 40
12
22
(T2) P1.0
(T2EX) P1.1
P1.2
P1.3
P1.4
P1.5
(SCL)P1.6
(SDA)P1.7
RESET
(RXD) P3.0
(TXD)P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
PRELIMINARY
MX10E8050I /
MX10E8050IA
Mnemonic
V
ss
V
cc
P0.0 ~ 0.7
Pin Number
PDIP
PLCC
20
22
40
44
39-32
43-36
Type
LQFP
16
38
37-30
I
I
I/O
Name and Function
Ground: 0 volt reference
Power Supply: This is the power supply voltage for normal,
idle and power-down operation
Port 0: Port 0 is an open drain, bi-directional I/O port. Port 0
pins have 1s written to them float and can be used as high
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accessed to external program
and data memory. In this application, it uses strong internal
pull-ups when emitting 1s.
Port1: Port 1 is an 8-bit bi-directional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Note that P1.6 and
P1.7 are open drain pins for I
2
C function.
Alternate functions for port 1 include:
T2(P1.0): Timer/Counter 2 external count input/clock out
T2EX(P1.1): Timer/Counter 2 Reload / Capture / Direction
control
SDA (P1.7): Data line for I
2
C
SCL (P1.6): Clock line for I
2
C
P1.0~1.7
1-8
2-9
40-44
1-3
I/O
1
2
3
4
5
6
7
8
21-28
2
3
4
5
6
7
8
9
24-31
40
41
42
43
44
1
2
3
18-25
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
P2.0~2.7
P3.0~3.7
10-17
11,
5,
I/O
Port 2 : Port 2 is an 8-bit bi-directional I/O port with internal
pull-ups. Port2 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull-ups. Port 2 emits the high
ordered address byte during fetches from external program
memory and during accesses to external data memory that
use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During
accesses to external data memory using 8-bit addresses
(MOVX@R
I
), port 2 emits the contents of P2 special
`function register.
Port 3: Port 3 is an 8-bit bi-directional I/O port with internal
P/N:PM0887
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.6, MAR. 28, 2005
4
PRELIMINARY
MX10E8050I /
MX10E8050IA
13-19
7-13
pull-ups. Port 3 pins that have 1s written to them are pulled
high with the internal pull-ups and can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves
the special features of MX10E8050I family, as listed below:
RxD (P3.0) : Serial input port
TxD (P3.1) : Serial output port
INT0 (P3.2) : External interrupt 0
INT1 (P3.3) : External interrupt 1
T0 (P3.4) : Timer 0 external input
T1 (P3.5) : Timer 1 external input
WR (P3.6) : External data memory write strobe
RD (P3.7) : External data memory read strobe
Port 4: Port 4 is an 4-bit bi-directional I/O port with internal
pull-ups. Port 4 pins that have 1s written to them are pulled
high with the internal pull-ups and can be used as inputs. As
inputs, Port 4 pins that are externally pulled low will source
current because of the internal pull-ups. Port 4 also serves
the special features of MX10E8050I family, as listed below:
PWM0 (P4.0) : PWM module output 0
PWM1 (P4.1) : PWM module output 1
PWM2 (P4.2) : PWM module output 2
PWM3 (P4.3) : PWM module output 3
Reset : A high on this pin for eight machine cycles while the
oscillator is running, reset the devices.
Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory. In
normal operation, ALE is emitted at constant rate of 1/6 the
oscillator frequency in 12x clock mode. 1/3 the oscillator
frequency in 6x clock mode, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory.
Program Strobe Enable: The read strobe to external program
memory. When executing code from external program
memory, PSEN is activated twice each machine cycle.,
except the two PSEN activation are skipped during each
access to external data memory. PSEN is not activated
during fetch from internal program memory.
External Access Enable/ Programming Supply Voltage: EA
must be external held low to enable the device to fetch code
from external program memory locations 0000H and FFFFH
for 64 K devices.
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier.
5
10
11
12
13
14
15
16
17
P4.0~P4.3
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
14
I
O
I
I
I
I
O
O
I/O
P4.0
P4.1
P4.2
P4.3
RST
ALE
9
30
23
34
1
12
10
33
17
28
39
6
4
27
I
I
I
I
I
O
PSEN
29
32
26
O
EA
31
35
15
I
XTAL 1
XTAL 2
P/N:PM0887
19
18
21
20
15
14
I
O
Specifications subject to change without notice, contact your sales representatives for the most update information.
REV. 1.6, MAR. 28, 2005
