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MX29F002/002N T/B

2M-BIT [256K x 8] CMOS FLASH MEMORY

FEATURES

•

262,144x 8 only

Fast access time: 55/70/90/120ns

Low power consumption

- 30mA maximum active current(5MHz)

- 1uA typical standby current

Programming and erasing voltage 5V ± 10%

Command register architecture

- Byte Programming (7us typical)

- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte

x1, and 64K-Byte x 3)

Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors or the

whole chip with Erase Suspend capability.

- Automatically programs and verifies data at specified

address

Erase Suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, a sector that is not being erased, then

resumes the erase operation.

Status Reply

- Data polling & Toggle bit for detection of program and

erase cycle completion.

Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

- Sector protect/unprotect for 5V only system or 5V/12V

system

100,000 minimum erase/program cycles

Latch-up protected to 100mA from -1 to VCC+1V

Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

Hardware RESET pin(only for 29F002T/B)

- Resets internal state machine to read mode

Low VCC write inhibit is equal to or less than 3.2V

Package type:

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

20 years data retention

•

GENERAL DESCRIPTION

The MX29F002T/B is a 2-mega bit Flash memory organ-

ized as 256K bytes of 8 bits only. MXIC's Flash memories

offer the most cost-effective and reliable read/write non-

volatile random access memory. The MX29F002T/B is

packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is

designed to be reprogrammed and erased in-system or in-

standard EPROM programmers.

The standard MX29F002T/B offers access time as fast as

55ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX29F002T/B has separate chip enable (CE) and output

enable (OE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F002T/B uses a command register to manage this

functionality. The command register allows for 100% TTL

level control inputs and fixed power supply levels during

erase and programming, while maintaining maximum

EPROM compatibility.

MXIC's Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields for

erase and programming operations produces reliable

cycling. The MX29F002T/B uses a 5.0V ± 10% VCC

supply to perform the High Reliability Erase and auto

Program/Erase algorithms.

The highest degree of latch-up protection is achieved with

MXIC's proprietary non-epi process. Latch-up protection is

proved for stresses up to 100 milliamps on address and

data pin from -1V to VCC + 1V.

P/N: PM0547

REV. 1.5, MAR. 28, 2005

MX29F002/002N T/B

PIN CONFIGURATIONS

32 PDIP

RESET

A16

A15

A12

GND

32 TSOP (TYPE 1)

NC on MX29F002NT/B

VCC

A17

A14

A13

A11

A10

A11

A13

A14

A17

VCC

(NC on MX29F002NT/B) RESET

A16

A15

A12

A10

GND

MX29F002T/B

(NORMAL TYPE)

32 PLCC

NC on MX29F002NT/B

RESET

VCC

A12

A15

A16

A17

SECTOR STRUCTURE

A17~A0

3FFFFH

3BFFFH

A14

A13

16 K-BYTE

(BOOT SECTOR)

K-BYTE

39FFFH

37FFFH

2FFFFH

1FFFFH

0FFFFH

00000H

MX29F002T/B

A11

A10

VSS

MX29F002T Sector Architecture

A17~A0

3FFFFH

2FFFFH

1FFFFH

0FFFFH

07FFFH

05FFFH

03FFFH

00000H

K-BYTE

PIN DESCRIPTION

SYMBOL

A0~A17

Q0~Q7

RESET

VCC

GND

PIN NAME

Address Input

Data Input/Output

Chip Enable Input

Write Enable Input

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

Power Supply Pin (+5V)

Ground Pin

16 K-BYTE

(BOOT SECTOR)

MX29F002B Sector Architecture

P/N: PM0547

REV. 1.5, MAR. 28, 2005

MX29F002/002N T/B

BLOCK DIAGRAM

WRITE

RESET

CONTROL

INPUT

LOGIC

HIGH VOLTAGE

MACHINE

(WSM)

PROGRAM/ERASE

STATE

X-DECODER

MX29F002

FLASH

ARRAY

ADDRESS

LATCH

A0~A17

AND

BUFFER

STATE

SENSE

AMPLIFIER

Y-DECODER

Y-PASS GATE

SOURCE

COMMAND

DATA

DECODER

PGM

DATA

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

P/N: PM0547

REV. 1.5, MAR. 28, 2005

MX29F002/002N T/B

AUTOMATIC PROGRAMMING

The MX29F002T/B is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical chip

programming time of the MX29F002T/B at room temperature

is less than 3.5 seconds.

cally pre-program and verify the entire array. Then the

device automatically times the erase pulse width, verifies

the erase, and counts the number of sequences. A status

bit similar to DATA polling and status bit toggling between

consecutive read cycles provides feedback to the user as

to the status of the programming operation.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as inputs to an internal state-machine which controls

the erase and programming circuitry. During write cycles,

the command register internally latches address and data

needed for the programming and erase operations. During

a system write cycle, addresses are latched on the falling

edge, and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29F002T/B electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of hot

electron injection.

During a program cycle, the state-machine will control the

program sequences and command register will not re-

spond to any command set. During a Sector Erase cycle,

the command register will only respond to Erase Suspend

command. After Erase Suspend is completed, the device

stays in read mode. After the state machine has com-

pleted its task, it will allow the command register to

respond to its full command set.

AUTOMATIC CHIP ERASE

Typical erasure at room temperature is accomplished in

less than 3 seconds. The device is erased using the

Automatic Erase algorithm. The Automatic Erase algorithm

automatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

internally controlled by the device.

AUTOMATIC SECTOR ERASE

The MX29F002T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically programs

the specified sector(s) prior to electrical erase. The timing

and verification of electrical erase are internally controlled

by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write a program set-up commands include 2

unlock write cycle and A0H and a program command

(program data and address). The device automatically

times the programming pulse width, verifies the program,

and counts the number of sequences. A status bit similar

to DATA polling and a status bit toggling between

consecutive read cycles, provides feedback to the user as

to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using standard

microprocessor write timings. The device will automati-

P/N: PM0547

REV. 1.5, MAR. 28, 2005

MX29F002/002N T/B

TABLE 1. SOFTWARE COMMAND DEFINITIONS

Command

Bus

Cycle

Reset

Read

Read Silicon ID

Sector Protect

Verification

Program

Chip Erase

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

protect/unprotect

Note:

1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).

DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't

care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated

with A11~A17 in either state.

4.For Sector Protect Verification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

555H AAH

XXXH B0H

XXXH 30H

555H AAH

2AAH 55H

555H 80H

555H AAH

2AAH 55H

555H 20H

2AAH 55H

555H A0H

555H 80H

First Bus

Cycle

Addr Data

XXXH F0H

2AAH 55H

555H 90H

ADI

(SA)

DDI

00H

Second Bus

Cycle

Addr Data

Third Bus

Cycle

Addr Data

Fourth Bus

Cycle

Addr Data

Fifth Bus

Cycle

Addr Data

Sixth Bus

Cycle

Addr Data

555H AAH

(X02H) 01H

2AAH

55H 555H 10H

55H SA

30H

555H AAH

COMMAND DEFINITIONS

Device operations are selected by writing specific address

and data sequences into the command register. Writing

incorrect address and data values or writing them in the

improper sequence will reset the device to the read mode.

Table 1 defines the valid register command sequences.

Note that the Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only while the Sector Erase

operation is in progress. Either of the two reset command

sequences will reset the device(when applicable).

P/N: PM0547

REV. 1.5, MAR. 28, 2005