PRELIMINARY
MX29F1615
16M-BIT [2M x8/1M x16] CMOS
SINGLE VOLTAGE FLASH EEPROM
FEATURES
•
•
•
•
•
5V
±
10% write and erase
JEDEC-standard EEPROM commands
Endurance:100 cycles
Fast access time: 90/100/120ns
Auto Erase and Auto Program Algorithms
- Automatically erases the whole chip
- Automatically programs and verifies data at
specified addresses
•
Status Register feature for detection of
program or erase cycle completion
•
Low VCC write inhibit is equal to or less than 3.2V
•
Software and hardware data protection
•
Page program operation
- Internal address and data latches for 64 words per
page
- Page programming time: 0.9ms typical
•
Low power dissipation
- 30mA typical active current
- 1uA typical standby current
•
CMOS and TTL compatible inputs and outputs
•
Package Type:
- 42 lead PDIP
GENERAL DESCRIPTION
The MX29F1615 is a 16-mega bit Flash memory organized
as either 1M wordx16 or 2M bytex8. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory. The
MX29F1615 is packaged in 42-pin PDIP. It is designed
to be reprogrammed and in standard EPROM
programmers.
The standard MX29F1615 offers access times as fast as
90ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the MX29F1615
has separate chip enables(CE) and output enable (OE)
control.
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The MX29F1615
uses a command register to manage this functionality.
The command register allows for 100% TTL level control
inputs and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
To allow for simple in-system reprogrammability, the
MX29F1615 requires high input voltages (10V) on BYTE/
VPP pin for programming. Reading data out of the device
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1615 uses a 5V
±
10% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N: PM0615
1
REV.1.2, NOV. 21, 2002
MX29F1615
PIN CONFIGURATIONS
42 PDIP(600mil)
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
PIN DESCRIPTION
SYMBOL
A0 - A19
Q0 - Q14
Q15/A - 1
CE
OE
BYTE/VPP
VCC
GND
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte mode)
Chip Enable Input
Output Enable Input
Word/Byte Selection Input/Write Enable
Input
Power Supply
Ground Pin
MX29F1615
P/N: PM0615
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REV. 1.2, NOV. 21, 2002
MX29F1615
BLOCK DIAGRAM
CE
OE
BYTE/VPP
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
COMMAND INTERFACE
REGISTER
X-DECODER
MX29F1615
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
(CIR)
ADDRESS
LATCH
Q15/A-1
A0-A19
AND
BUFFER
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PAGE
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N: PM0615
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REV. 1.2, NOV. 21, 2002
MX29F1615
Table1.PIN DESCRIPTIONS
SYMBOL
A0 - A19
Q0 - Q7
TYPE
INPUT
INPUT/OUTPUT
NAME AND FUNCTION
ADDRESS INPUTS: for memory addresses. Addresses are internally latched
during a write cycle.
LOW-BYTE DATA BUS: Input data and commands during Command Interface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriate read mode. Floated when the chip is de-selected or the outputs are
disabled.
Q8 - Q14
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs
array, identifier data in the appropriate read mode; not used for status register
reads. Floated when the chip is de-selected or the outputs are disabled
Q15/A -1
CE
INPUT/OUTPUT
INPUT
Selects between high-byte data INPUT/OUTPUT(BYTE/VPP = HIGH) and LSB
ADDRESS(BYTE/VPP = LOW) for read operation.
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the device is de-selected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device. Device
selection occurs with the latter falling edge of CE. The first rising edge of CE
disables the device.
OE
BYTE/VPP
INPUT
INPUT
OUTPUT ENABLES: Gates the device's data through the output buffers during a
read cycle OE is active low.
BYTE ENABLE: While operating read mode, BYTE/VPP Low places device in x8
mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A-
1 selects between the high and low byte. While operating read mode, BYTE/VPP
high places the device in x16 mode, and turns off the Q15/A-1 input buffer.
Address A0, then becomes the lowest order address. Write Enable is active while
apply 10V on the BYTE/VPP pin.
VCC
GND
DEVICE POWER SUPPLY(5V±10%)
GROUND
P/N: PM0615
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REV. 1.2, NOV. 21, 2002
MX29F1615
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
Table2.1 Bus Operations
Mode
Read
Output Disable
Standby
Manufacturer ID
Device ID
MX29F1615
Write
Notes
1,5
1
1
2,4
2,4
CE
VIL
VIL
VIH
VIL
VIL
OE
VIL
VIH
X
VIL
VIL
BYTE/VPP
VIH/VIL
VIH/VIL
X
VIH/VIL
VIH/VIL
A0
X
X
X
VIL
VIH
A1
X
X
X
VIL
VIL
A9
X
X
X
VID
VID
Q0-Q7
DOUT
High Z
X
C2H
6BH
Q8-Q14
HighZ/DOUT
HIghZ
X
High Z/00H
High Z/00H
Q15/A-1
VIL/VIH/DOUT
High Z/X
X
VIL/OB
VIL/OB
1,3,6
VIL
VIH
VHH
X
X
X
DIN
DIN
DIN
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes.
3. Commands for different Erase operations or Data program operations can only be successfully completed through proper command
sequence.
4. VID = 11.5V- 12.5V.
5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
6.VHH=9.5V~10.5V
P/N: PM0615
5
REV. 1.2, NOV. 21, 2002
