PRELIMINARY
MX29LV004T/B
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55R/70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (9us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
- 40-pin TSOP
- 32-pin PLCC
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV004T/B is a 4-mega bit Flash memory or-
ganized as 512K bytes of 8 bits. MXIC's Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The MX29LV004T/
B is packaged in 40-pin TSOP and 32-pin PLCC. It is
designed to be reprogrammed and erased in system or
in standard EPROM programmers.
The standard MX29LV004T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV004T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV004T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV004T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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1
MX29LV004T/B
PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
NC
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE
VSS
CE
A0
MX29LV004T/B
32 PLCC
VCC
A12
A15
A16
A18
A17
WE
PIN DESCRIPTION
SYMBOL
A0~A18
A14
A13
A8
A9
9
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Hardware Reset Pin/Sector Protect Unlock
(for 40-TSOP)
A7
A6
A5
A4
A3
A2
A1
A0
Q0
5
4
1
32
30
29
Q0~Q7
CE
WE
RESET
MX29LV004T/B
25
A11
OE
A10
CE
13
14
Q1
Q2
GND
17
Q3
Q4
Q5
21
20
Q6
Q7
OE
RY/BY
VCC
GND
Output Enable Input
Ready/Busy Output (for 40-TSOP)
Power Supply Pin (2.7V~3.6V)
Ground Pin
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2
MX29LV004T/B
BLOCK STRUCTURE
Table 1: MX29LV004T SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
16Kbytes
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-77FFF
78000-79FFF
7A000-7BFFF
7C000-7FFFF
A18 A17
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
Sector Address
A16
0
1
0
1
0
1
0
1
1
1
1
A15
X
X
X
X
X
X
X
0
1
1
1
A14
X
X
X
X
X
X
X
X
0
0
1
A13
X
X
X
X
X
X
X
X
0
1
X
Table 2: MX29LV004B SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
A18 A17
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
Sector Address
A16
0
0
0
0
1
0
1
0
1
0
1
A15
0
0
0
1
X
X
X
X
X
X
X
A14
0
1
1
X
X
X
X
X
X
X
X
A13
X
0
1
X
X
X
X
X
X
X
X
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3
MX29LV004T/B
BLOCK DIAGRAM
CE
OE
WE
RESET
(for 40-TSOP)
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
MX29LV004T/B
X-DECODER
REGISTER
ARRAY
SOURCE
HV
ADDRESS
LATCH
A0-A18
FLASH
ARRAY
Y-PASS GATE
AND
BUFFER
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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4
MX29LV004T/B
AUTOMATIC PROGRAMMING
The MX29LV004T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV004T/B is less than 10 sec-
onds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV004T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV004T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
The device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro-
gram a byte, instead of four. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the sta-
tus of the programming operation. Refer to write opera-
tion status, table7, for more information on these status
bits.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0. This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1 as referring to Table
3. In addition, to access the automatic select codes in-
system, the host can issue the automatic select com-
P/N:PM0732
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5
微控制器 MCU
