MX29LV640T/B
FEATURES
64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY
FLASH MEMORY
SOFTWARE FEATURES
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from
or program data to another sector which is not being
erased
• Status Reply
- Data polling & Toggle bits provide detection of pro-
gram and erase operation completion
GENERAL FEATURES
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
• 8,388,608 x 8 / 4,194,304 x 16 switchable
• Sector structure
- 8KB (4KW) x 8 and 64KB(32KW) x 127
• Sector Protection/Chip Unprotect
- Provides sector group protect function to prevent
program or erase operation in the protected sector
group
- Provides chip unprotect function to allow code
changes
- Provides temporary sector group unprotect function
for code changes in previously protected sector groups
• Secured Silicon Sector
- Provides a 128-word area for code or data that can
be permanently protected.
- Once this sector is protected, it is prohibited to pro-
gram or erase within the sector again.
• Latch-up protected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit is equal to or less than 1.5V
• Compatible with JEDEC standard
- Pin-out and software compatible to single power sup-
ply Flash
PERFORMANCE
• High Performance
- Fast access time: 90/120ns
- Fast program time: 11us/word, 45s/chip (typical)
- Fast erase time: 0.9s/sector, 45s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 0.2uA (typ.)
• Minimum 100,000 erase/program cycle
• 20-year data retention
HARDWARE FEATURES
• Ready/Busy (RY/BY) Output
- Provides a hardware method of detecting program
and erase operation completion
• Hardware Reset (RESET) Input
- Provides a hardware method to reset the internal
state machine to read mode
• WP Pin
- Write protect (WP) function allows protection of two
outermost boot sectors, regardless of sector protect
status
PACKAGE
• 48-pin TSOP
• 63-ball CSP
• 64-ball Easy BGA
GENERAL DESCRIPTION
The MX29LV640T/B is a 64-mega bit Flash memory or-
ganized as 8M bytes of 8 bits or 4M bytes of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29LV640T/B is packaged in 48-pin TSOP, 63-
ball CSP and 64-ball Easy BGA. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV640T/B offers access time as fast
as 90ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV640T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
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MX29LV640T/B
MX29LV640T/B uses a command register to manage this
functionality.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and program
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable
cycling. The MX29LV640T/B uses a 2.7V to 3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
AUTOMATIC SECTOR ERASE
The MX29LV640T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29LV640T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING
The MX29LV640T/B is byte/word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the
data programmed. The typical chip programming time at
room temperature of the MX29LV640T/B is less than 50
seconds.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 115 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
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MX29LV640T/B
PIN CONFIGURATION
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
A21
WP
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
MX29LV640T/B
63 Ball CSP (Top View, Ball Down)
12.0 mm
8
NC
NC
NC*
NC*
7
NC
NC
A13
A12
A14
A15
A16
BYTE
Q15/
A-1
GND
NC*
NC*
6
A9
A8
A10
A11
Q7
Q14
Q13
Q6
5
WE
RESET
A21
A19
Q5
Q12
VCC
Q4
11.0 mm
4
RY/BY
WP
A18
A20
Q2
Q10
Q11
Q3
3
A7
A17
A6
A5
Q0
Q8
Q9
Q1
2
NC*
A3
A4
A2
A1
A0
CE
OE
GND
NC*
NC*
1
NC*
NC*
NC*
NC*
A
B
C
D
E
F
G
H
J
K
L
M
* Ball are shorted together via the substrate but not connected to the die.
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MX29LV640T/B
64 Ball Easy BGA (Top View, Ball Down)
A8
NC
A7
A13
A6
A9
A5
WE
A4
RY/BY
A3
A7
A2
A3
A1
NC
B8
NC
B7
A12
B6
A8
B5
RESET
B4
WP
B3
A17
B2
A4
B1
NC
C8
NC
C7
A14
C6
A10
C5
A21
C4
A18
C3
A6
C2
A2
C1
NC
D8
NC
D7
A15
D6
A11
D5
A19
D4
A20
D3
A5
D2
A1
D1
NC
E8
GND
E7
A16
E6
Q7
E5
Q5
E4
Q2
E3
Q0
E2
A0
E1
NC
F8
NC
F7
BYTE
F6
Q14
F5
Q12
F4
Q10
F3
Q8
F2
CE
F1
NC
G8
NC
G7
Q15
G6
Q13
G5
VCC
G4
Q11
G3
Q9
G2
OE
G1
NC
H8
NC
H7
GND
H6
Q6
H5
Q4
10 mm
H4
Q3
H3
Q1
H2
GND
H1
NC
13mm
PIN DESCRIPTION
SYMBOL
A0~A21
Q0~Q14
Q15/A-1
CE
WE
OE
RESET
WP
RY/BY
VCC
GND
NC
PIN NAME
Address Input
Data Inputs/Outputs
Q15(Word Mode)/LSB addr(Byte Mode)
Chip Enable Input
Write Enable Input
Output Enable Input
Hardware Reset Pin, Active Low
Hardware Write Protect
Read/Busy Output
+3.0V single power supply
Device Ground
Pin Not Connected Internally
LOGIC SYMBOL
22
A0-A21
Q0-Q15
(A-1)
16 or 8
CE
OE
WE
RESET
WP
RY/BY
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MX29LV640T/B
BLOCK DIAGRAM
CE
OE
WE
WP
BYTE
RESET
WRITE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29LV640T/B
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A21
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
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