MX29SL800C T/B
MX29SL802C T/B
8M-BIT [1M x 8 / 512K x 16] SINGLE VOLTAGE
1.8V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Single Power Supply Operation
- 1.65 to 2.2 volt for read, erase, and program operations
• 1,048,576 x 8 / 524,288 x 16 switchable
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Sector Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 15
• Sector protection
- Hardware method to disable any combination of sectors from program or erase operations
- Temporary sector unprotected allows code changes in previously locked sectors
• Latch-up protected to 100mA from -1V to Vcc + 1V
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Access time: 90ns
- Byte/Word program time: 12us/18us (typical)
- Erase time: 1.3s/sector, 18s/chip (typical)
• Low Power Consumption
- Low active read current: 6mA (maximum) at 5MHz
- Low standby current: 1uA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (LFBGA/TFBGA/WFBGA)
• 48-Ball XFLGA
•
All Pb-free devices are RoHS Compliant
P/N:PM1244
REV. 2.0, NOV. 20, 2008
1
MX29SL800C T/B
MX29SL802C T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48-Ball CSP( Ball Pitch = 0.8 mm), Top View, Balls Facing Down
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RE-
SET#
NC
NC
Q5
Q12
VCC
Q4
3
RY/BY#
NC
A18
NC
Q2
Q10
Q11
Q3
2
A7
A17
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE#
OE#
GND
1
A
B
C
D
E
F
G
H
P/N:PM1244
REV. 2.0, NOV. 20, 2008
2
MX29SL800C T/B
MX29SL802C T/B
48-Ball XFLGA (Land Pitch = 0.5mm, Package Height = 0.5mm), Top View, Balls Facing Down
6
A2
A4
A6
A17
NC
NC
WE#
RE-
SET#
A9
A11
5
A1
A3
A7
NC
NC
A10
A13
A14
4
A0
A5
A18
A8
A12
A15
3
CE#
Q8
Q10
Q4
Q11
A16
2
GND
OE#
Q9
BYTE#
NC
Q5
Q6
Q7
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
1
Q15/
A-1
GND
A
B
C
D
E
F
G
H
J
K
L
48-Ball WFBGA (Balls Facing Down, 4 x 6 x 0.75 mm for 29SL802C)
6
A2
A4
A6
A17
NC
NC
WE#
NC
A9
A11
5
A1
A3
A7
NC
NC
A10
A13
A14
4
A0
A5
A18
A8
A12
A15
3
CE#
Q8
Q10
Q4
Q11
A16
2
GND
OE#
Q9
NC
NC
Q5
Q6
Q7
1
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15
GND
A
B
C
D
E
F
G
H
J
K
L
P/N:PM1244
REV. 2.0, NOV. 20, 2008
3
MX29SL800C T/B
MX29SL802C T/B
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18
Q0~Q14
Q15/A-1
CE#
WE#
BYTE#
RESET#
OE#
RY/BY#
VCC
GND
Address Input
Data Input/Output
Q15 (data input/output, word mode)/
A-1(LSB address input, byte mode)
Chip Enable Input
Write Enable Input
Word/Byte Selection input
Hardware Reset Pin
Output Enable Input
Ready/Busy Output
Power Supply Pin (1.65V~2.2V)
Ground Pin
LOGIC SYMBOL
19
A0-A18
Q0-Q15
(A-1)
16 or 8
CE#
OE#
WE#
RESET#
RY/BY#
BYTE#
P/N:PM1244
REV. 2.0, NOV. 20, 2008
4
MX29SL800C T/B
MX29SL802C T/B
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
BYTE#
WRITE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
STATE
FLASH
ARRAY
ARRAY
REGISTER
ADDRESS
LATCH
A0-AM
AND
BUFFER
SENSE
AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
P/N:PM1244
REV. 2.0, NOV. 20, 2008
5
