MX93000C
FEATURES
. Single +5V power supply PCM CODEC
. Support £g/A law and 16-bit format linear data
. Support switch paths for DAM (digital answering
machine) related product application
. Support power-low and battery-low detectors
. Support power on reset function for DSP and MCU
use
. Support external volume control
. On-chip differential line driver
. On-chip ALC (automatic level control)
. On-chip digital volume control
. On-chip programmable receive/transmit gain control
. Easy interface to general purpose DSP
. Easy Read/Write of control registers by MCU
. Easy interface to FAX or Cordless phone
. Automatic power-down function
. Support 2.048 or 1.536MHz master clock
. Support smart power management
. 28-pin SOP/DIP package
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDATA
SDENB
DX
DR
FS
MCLK
VDD
DGND
PRST
BATB
VBAT
POWB
VPOW
LIN
SPK
VR
VREF
FILT
ALCC2
ALCRC
ALCC1
AUX
MIC
AG
AGND
AVDD
LOUTN
LOUTP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28 PINS SOP/DIP
P/N:PM0687
REV. 1.0, DEC. 07, 1999
1
MX93000C
PRODUCT OVERVIEW
The MX93000C PCM CODEC integrates key functions of the analog-front-end of Digital Answering Machine (DAM)
related products into an integrated circuit. The MX93000C PCM CODEC is especially powerful when applied to
some DAM models which are intended to meet different countries' specifications in the same system hardware. User
can achieve this goal by simply setting control firmware. This benefit will help DAM system makers to save develop-
ing time and R&D resources.
The MX93000C has one A/D, D/A converter so as to meet the requirement of the DAM application. The on-chip
digital filters, which are carried out with 16-bit and 2's complement format, are used to get required frequency
response of a PCM CODEC. The CODEC can support 8-bit u/A law and linear data format. For the latter, it is 16-bit
format with 14-bit resolution.
Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a
built-in Automatic Level Control (ALC) and PRE-Programmable Gain Amplifier (PRE-PGA). The
ALC
circuit controls
the signal level about 1.2Vpp, so as to get a better signal to noise ratio during a low-level input. The
PRE-PGA
circuit is used to control the gain of different sources like
MIC, AUX
or
LIN
input.
After the digital data is converted into analog signal by D/A converter, a fully differential line driver is supported to
drive the telephone line directly without needing any external amplifiers. Besides, the analog signal can be monitored
by passing the on-chip volume control or external volume control.
The MX93000C supports many switches as well. User can program the control registers of the PCM CODEC to
accomplish all specific operations of DAM related products.
In order to let MCU (Micro controller) easily Read/Write the control registers of the MX93000C, the sampling clock of
the serial control data is clocked by
FS
clock and synchronized by
SDENB,
where
SDENB
signal is coming from the
MCU output port by detecting one of the rising edge of external
FS
clock.
P/N:PM0687
REV. 1.0, DEC. 07, 1999
2
MX93000C
BLOCK DIAGRAM
AVD
D
AUX- I/O
F A RXA
X
Cor dl essp ho ne R
XA
25
F ILT
VREF
26
VREF
AG
AVD
D
AGND
17
18
C8
C10
VDD
C9
AGND
7
8
DGND
VDD
DGND
S WI
R2
S WA
C4
20
MI C
S WC
b
a
A
LI N
P GA
S WD
PCM CODEC
AIN
a
b
MIC
C14
14
AUX
L IN
A
c
d
PRE
PGA
MCL K
6
DSP
Ma ster
Clo ck
sig na l
DSP
F ram e
Sync .
si gn al
DSP
T ran smi t
DATA
DSP
Recei ve
DATA
AG
ALC
S WJ
S WL
S WB
FS
5
DR
23
C7
ALCRC
ALCC1
ALCC2
DX
22
C6
24
4
+
R3
3
AOUT
15
L OUTP
L OUTN
S WE
LI N
DRV
FS
TE LE PHONE LINE
I NT ERFACE
16
S WG
b
a
S WF
A
ATT 1
S ERIAL
CONTROL
UNIT
SDENB
2
uP
Ena ble
SDATA
uP
T X / RX
Co ntrol
D A
AT
uP
ch eck
SYST EM
Powe r
uP
ch eck
SYST EM
Batt ery
SPK
C1
POWER
AM P
VR1
28
SPK
SDA A
T
1
ATT 2
1.2 5V
POW
POWB
12
S WK
27
VR
S WH
BAT
1.2 5V
OR
BATB
10
19
C2
AG
AG
u P/DSP
Powe r On
Reset
AUX
AUX
21
AUX- I/O
F A T XA
X
Cor dl essp ho ne TXA
AC/DC
ADAPT OR
R4
R5
VPO W
13
BATT ERY
POWER
R6
R8
R7
C11
D1
VBA
T
11
PRST
9
P/N:PM0687
REV. 1.0, DEC. 07, 1999
3
MX93000C
PIN DESCRIPTION
SYMBOL PIN TYPE
SDATA
SDENB
DX
DR
FS
MCLK
VDD
DGND
PRST
BATB
VBAT
POWB
VPOW
LIN
LOUTP
LOUTN
AVDD
AGND
AG
MIC
AUX
ALCC1
ALCRC
ALCC2
FILT
VREF
VR
SPK
I/O (D)
I (D)
O (D)
I (D)
I (D)
I (D)
P (D)
P (D)
O (D)
O (A)
I (A)
O (A)
I (A)
I (A)
O (A)
O (A)
P(A)
P(A)
O (A)
I (A)
I/O (A)
O (A)
O (A)
O (A)
I/O (A)
O (A)
O (A)
O (A)
PIN No.
DIP/SOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DESCRIPTION
Bi-directional serial control data port; it is an interface for Micro processor
to Transmit / Receive serial control data
the enabled signal for serial control data; active low; to start to Receive/
Transmit serial ontrol data (A2~A0,D7~D0)
transmit serial data
receive serial data
frame sync. Input; 8KHz frame sync. clock for the Transmit/Receive serial
data
master clock input, if MCLK is continuously high or low then the MX93000C
will get into power down mode automatically
digital power supply; 5V power supply for all internal digital logic
digital power ground
power on reset (active high); please refer to the description of power
management in FUNCTIONAL DESCRIPTION
the output of BAT comparator; active low
the non-inverting input of BAT comparator; the voltage is divided from bat
tery power for comparison with 1.25V
; with 7V surge protection
the output of POW comparator; active low
the non-inverting input of POW comparator; the voltage is divided from
system DC power for comparison with 1.25V
; with 7V surge protection
telephone line signal input with PRE-PGA; PGA from 0 to 22.5dB;
see NOTE 1
the non-inverting output of LIN-DRV with PGA; PGA from 0 to 22.5dB;
1.5dB/step
the inverting output of LIN-DRV with PGA; PGA from 0 to 22.5dB; 1.5dB/
step
analog power supply; 5V power supply for all internal analog circuits
analog power ground
internal analog signal ground; nominal 2.25V
and should not be used to
sink or source current
microphone input with PRE-PGA; PGA from 0 to 22.5dB; see NOTE 1
1. auxiliary signal input with PRE-PGA; PGA from 0 to 22.5dB; see NOTE 1
2. as an I/O port for SWK and SWH
automatic level control (ALC) DC blocking capacitor output
automatic level control (ALC) time constant; see FIG. 9 and FIG. 10
automatic level control (ALC) DC blocking capacitor input
1. anti-aliasing filter; 2. as an I/O port for AIN (A/D input)
voltage reference; nominal 2.25V
and can sink 450uA
external speaker volume control; use a 10Kohm variable resistor
Speaker output ; it can be attenuated by VR or control register from 0 to
-45dB
@ PIN TYPE : "I" : Input Port; "O" : Output Port; "I/O" : Bi-direction Port; "P" : Power; "(D)" : Digital Pin; "(A)" : Analog Pin
P/N:PM0687
REV. 1.0, DEC. 07, 1999
4
MX93000C
BASIC COMPONENTS REQUIRED
REFERANCE PART
R2
2Kohm
R3
R4,R5
R6,R7
R8
C1,C4,C14
C2,C9,C10
C6
C7
*C8
C11
*VR1
D1
560Kohm
DESCRIPTION
current limit resistor; to limit MIC bias current; please follow MIC specification
ALC release time constant; see FIG. 10
to scale down DC power supply (VPOW) for reference to 1.25V to check power-low
to scale down battery power (VBAT) for reference to 1.25V
to check battery-low
time constant for power-on-reset circuits ; where RC=R8 * C11
DC blocking capacitor (0.1~10uF)
De-couple capacitor ( 0.1~10uF)
DC blocking capacitor (0.1~10uF);
H.P.F. 3dB point : fc
1/2
* 4.4Kohm * C6 (0.22uF) = 164Hz
ALC attack time constant; see FIG. 9
anti-aliasing capacitor
time constant for power-on-reset circuits ; where RC=R8 * C11
to attenuate the input signal from SWH or SWF, if using digital volume control, then it
does not need resistor VR1
to protect reset circuits from spike
10Kohm
0.1uF
0.1uF
0.22uF
10uF
1000pF
10uF
10Kohm
1N4148
@ where " * " mark shows that the required component cannot be changed.
P/N:PM0687
REV. 1.0, DEC. 07, 1999
5
单片机
