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MXD1005UA100

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, UMAX-8

器件类别:逻辑    逻辑   

厂商名称:Maxim(美信半导体)

厂商官网:https://www.maximintegrated.com/en.html

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Maxim(美信半导体)
零件包装代码
SOIC
包装说明
UMAX-8
针数
8
Reach Compliance Code
_compli
系列
1000
JESD-30 代码
S-PDSO-G8
JESD-609代码
e0
长度
3 mm
逻辑集成电路类型
SILICON DELAY LINE
功能数量
1
抽头/阶步数
5
端子数量
8
最高工作温度
85 °C
最低工作温度
-40 °C
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP8,.19
封装形状
SQUARE
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)
245
电源
5 V
最大电源电流(ICC)
70 mA
可编程延迟线
NO
Prop。Delay @ Nom-Su
100 ns
认证状态
Not Qualified
座面最大高度
1.1 mm
最大供电电压 (Vsup)
5.25 V
最小供电电压 (Vsup)
4.75 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总延迟标称(td)
100 ns
宽度
3 mm
文档预览
19-1309; Rev 0; 10/97
5-Tap Silicon Delay Line
_______________General Description
The MXD1005 silicon delay line offers five equally
spaced taps with delays ranging from 12ns to 250ns
and a nominal accuracy of ±2ns or ±3%, whichever is
greater. Relative to hybrid solutions, this device offers
enhanced performance and higher reliability, and
reduces overall cost. Each tap can drive up to ten 74LS
loads.
The MXD1005 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin µMAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1005 and other delay line products.
____________________________Features
o
Improved Second Source to DS1005
o
Available in Space-Saving 8-Pin µMAX Package
o
17mA Supply Current vs. Dallas’ 40mA
o
Low Cost
o
Delay Tolerance of ±2ns or ±3%, whichever is
Greater
o
TTL/CMOS-Compatible Logic
o
Leading- and Trailing-Edge Accuracy
o
Custom Delays Available
MXD1005
________________________Applications
Clock Synchronization
Digital Systems
______________Ordering Information
PART
MXD1005C/D__
MXD1005PA__
MXD1005PD__
MXD1005SA__
MXD1005SE__
MXD1005UA__
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
Dice*
8 Plastic DIP
14 Plastic DIP
8 SO
16 Narrow SO
8 µMAX
_________________Pin Configurations
TOP VIEW
IN
1
TAP2
2
8
7
V
CC
TAP1
TAP3
TAP5
*Dice
are tested at T
A
= +25°C.
Note:
To complete the ordering information, fill in the blank with
the part number extension from the Part Number and Delay
Times table to indicate the desired delay per output.
MXD1005
TAP4
3
6
5
GND
4
_____Part Number and Delay Times
PART NUMBER
EXTENSION
(MXD1005_ _ __)
DELAY (t
PHL
, t
PLH
) PER OUTPUT (ns)
TAP4
TAP1
12
15
20
25
30
35
40
50
TAP2
24
30
40
50
60
70
80
100
TAP3
36
45
60
75
90
105
120
150
TAP4
48
60
80
100
120
140
160
200
TAP5
60
75
100
125
150
175
200
250
DIP/SO/µMAX
IN 1
N.C.
N.C.
2
3
14 V
CC
13 N.C.
12 TAP1
60
75
100
125
150
175
200
250
TAP2 4
N.C. 5
TAP4 6
GND 7
MXD1005
11 N.C.
10 TAP3
9
8
N.C.
TAP5
DIP
Note:
Contact factory for characterization data.
Functional Diagram appears at end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
5-Tap Silicon Delay Line
MXD1005
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ..............................................................-0.5V to +6V
All Other Pins..............................................-0.5V to (V
CC
+ 0.5V)
Short-Circuit Output Current (1sec) ....................................50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) ......727mW
14-Pin Plastic DIP (derate 10.0mW/°C above +70°C) ..800mW
8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW
16-Pin Narrow SO (derate 8.7mW/°C above +70°C) ....696mW
8-Pin µMAX (derate 4.1mW/°C above +70°C) .............330mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +5.0V ±5%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Supply Voltage
Input Voltage High
Input Voltage Low
Input Leakage Current
Active Current
Output Current High
Output Current Low
Input Capacitance
SYMBOL
V
CC
V
IH
V
IL
I
L
I
CC
I
OH
I
OL
C
IN
(Note 2)
(Note 2)
(Note 2)
0V
V
IN
V
CC
V
CC
= 5.25V, period = minimum (Notes 3, 4)
V
CC
= 4.75V, V
OH
= 4.0V
V
CC
= 4.75V, V
OL
= 0.5V
T
A
= +25°C (Note 5)
12
5
10
-1
17
CONDITIONS
MIN
4.75
2.2
0.8
1
70
-1
TYP
5.00
MAX
5.25
UNITS
V
V
V
µA
mA
mA
mA
pF
TIMING CHARACTERISTICS
(V
CC
= +5.0V ±5%, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Input Pulse Width
Input-to-Tap Delay
(leading edge)
Input-to-Tap Delay
(trailing edge)
Power-Up Time
Period
Note 1:
Note 2:
Note 3:
Note 4:
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
(Note 6)
4(t
WI
)
CONDITIONS
(Note 6)
(Notes 7–10)
(Notes 7–10)
MIN
40% of TAP5
t
PLH
See
Part Number and
Delay Times
table
See
Part Number and
Delay Times
table
100
TYP
MAX
UNITS
ns
ns
ns
ms
ns
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Specifications to -40°C are guaranteed by design, not production tested.
All voltages referenced to GND.
Measured with outputs open.
I
CC
is a function of frequency and TAP5 delay. Only an MXD1005_ _60 operating with a 40ns period and V
CC
= +5.25V will
have a maximum I
CC
of 70mA. For example, an MXD1005_ _100 will not exceed 30mA. See Supply Current vs. Input
Frequency graph in
Typical Operating Characteristics.
Guaranteed by design.
Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.).
V
CC
= +5V at +25°C. Typical delays are accurate on both rising and falling edges within ±2ns or ±3%.
See
Test Conditions
section.
The combination of temperature variations from +25°C to 0°C or +25°C to +70°C and voltage variation from 5.0V to 4.75V
or 5.0V to 5.25V may produce an additional typical input-to-tap delay shift of ±1.5ns or ±4%, whichever is greater.
All taps and outputs delays tend to vary unilaterally with temperature or supply variations. For example, if TAP1 slows
down, all other taps will also slow down; TAP3 cannot be faster than TAP2.
2
_______________________________________________________________________________________
5-Tap Silicon Delay Line
__________________________________________Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25°C, unless otherwise noted.)
MXD1005
ACTIVE CURRENT
vs. FREQUENCY
50% DUTY CYCLE
17
ACTIVE CURRENT (mA)
16
15
14
13
12
11
MXD1005_ _200
10
0.001
0.01
0.1
FREQUENCY (MHz)
1
10
MXD1005_ _75
MXD1005 TOC4
MXD1005_ _75
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
1.5
% CHANGE IN DELAY (TAP2)
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
RELATIVE TO NOMINAL (+25°C)
t
PHL
t
PLH
t
PLH
t
PHL
MXD1005 TOC1
18
2.0
MXD1005_ _100 TO MXD1005_ _200
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1005 TOC2
MXD1005_ _250
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
1.5
% CHANGE IN DELAY (TAP2)
1.0
0.5
0
-0.5
t
PLH
-1.0
-1.5
-2.0
RELATIVE TO NOMINAL (+25°C)
-40
-20
0
20
40
60
80
100
t
PHL
t
PHL
t
PLH
MXD1005 TOC3
2.0
1.5
% CHANGE IN DELAY (TAP2)
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-40
-20
0
20
40
60
80
RELATIVE TO NOMINAL (+25°C)
t
PHL
t
PLH
t
PLH
t
PHL
2.0
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
5-Tap Silicon Delay Line
MXD1005
______________________________________________________________Pin Description
PIN
8-PIN
DIP/SO/µMAX
1
2
3
4
5
6
7
8
14-PIN DIP
1
4
6
7
8
10
12
14
2, 3, 5, 9, 11,
13
16-PIN SO
1
4
6
8
9
11
13
16
2, 3, 5, 7, 10,
12, 14, 15
NAME
IN
TAP2
TAP4
GND
TAP5
TAP3
TAP1
V
CC
N.C.
Signal Input
40% of specified maximum delay
80% of specified maximum delay
Device Ground
100% of maximum specified delay
60% of specified maximum delay
20% of specified maximum delay
Power-Supply Input
No Connection. Not internally connected.
FUNCTION
Note:
Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________Definitions of Terms
Period:
The time elapsed between the first pulse’s
leading edge and the following pulse’s leading edge.
Pulse Width (t
WI
):
The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
Input Rise Time (t
RISE
):
The time elapsed between
the 20% and 80% points on the input pulse’s leading
edge.
Input Fall Time (t
FALL
):
The time elapsed between
the 80% and 20% points on the input pulse’s trailing
edge.
Time Delay, Rising (t
PLH
):
The time elapsed between
the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.
Time Delay, Falling (t
PHL
):
The time elapsed between
the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.
____________________Test Conditions
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
+25°C ±3°C
+5V ±0.01V
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance:
50Ω max
Rise and Fall Times:
3.0ns max
Pulse Width:
500ns max
Period:
1µs
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
4
_______________________________________________________________________________________
5-Tap Silicon Delay Line
MXD1005
V
CC
(+5V)
PERIOD
0.1µF
TIME
MEASUREMENT
UNIT
t
RISE
V
IH
IN
V
IL
2.4V
1.5V
0.6V
t
FALL
2.4V
1.5V
0.6V
1.5V
IN
50Ω
20%
TAP1
t
WI
20%
TAP2
t
PHL
MXD1005
20%
TAP3
t
PLH
20%
TAP4
1.5V
OUT
1.5V
20%
TAP5
74FO4
Figure 1. Timing Diagram
Figure 2. Test Circuit
__________Applications Information
Supply and Temperature
Effects on Delay
Variations in supply voltage may affect the MXD1005’s
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temper-
ature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.
Capacitance and Loading
Effects on Delay
The output load can affect the tap delays. Larger
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.
Board Layout Considerations/Decoupling
The device should be driven with a source that can
deliver the required current for proper operation. A
0.1µF ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capaci-
tance.
_______________________________________________________________________________________
5
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