NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N16D1633LPA
Advance Information
512K × 16 Bits × 2 Banks Low Power Synchronous DRAM
DESCRIPTION
These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288
words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the
clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally
pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Features
• JEDEC standard 3.0V/3.3V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVTTL interface.
• 4K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control.
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode
• All inputs and outputs referenced to the positive
edge of the system clock.
• Data mask function by DQM.
• Internal dual banks operation.
• Burst Read Single Write operation.
• Special Function Support.
-PASR (Partial Array Self Refresh)
-Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT
Auto Precharge Mode and controlled Precharge
Table 1: Ordering Information
PART NO.
N16D1633LPAZ2-75I
N16D1633LPAZ2-10I
N16D1633LPAC2-60I
N16D1633LPAC2-75I
N16D1633LPAC2-10I
N16D1633LPAT2-60I
N16D1633LPAT2-75I
N16D1633LPAT2-10I
CLOCK Freq.
133MHz
100MHz
166MHz
133MHz
100MHz
166MHz
133MHz
100MHz
-25
o
C to
85
o
C
3.0V/3.0V
or
3.3V/3.3V
Temperature
VDD/VDDQ
INTERLEAVE
PACKAGE
48-Ball Green
FBGA
60-Ball Green
WBGA
50-Pin Green
TSOP II
LVTTL
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
N16D1633LPA
NanoAmp Solutions, Inc.
Figure 1: Package Configuration (60-Ball WBGA)
6.4 0.1
1.25
3.9
0.65
Unit [mm]
Advance Information
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
2
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
3
4
5
6
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
NC
LDQM
/RAS
NC
NC
A0
A2
A3
7
VDD
A
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
/WE
/CAS
/CS
NC
A10
A1
0.65
0.65
B
C
D
E
F
G
10.1 0.1
10.1 0.1
H
J
K
L
M
N
P
R
9.1
9.1
0.3 0.05
7
6
5
4
3
2
1
VDD
[Top View]
[Bottom View]
1.0max
0.23 0.05
Note:
1. All Dimensions in millimeters
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
N16D1633LPA
NanoAmp Solutions, Inc.
Figure 2: Package Configuration (48-Ball FBGA)
6.0 0.1
1.125
3.75
0.75
Unit [mm]
Advance Information
1
A
B
C
D
E
F
G
H
CLK
DQ8
DQ9
VSS
VDD
DQ14
DQ15
NC
2
/CS
NC
DQ10
DQ11
DQ12
DQ13
NC
A8
3
A0
A3
A5
/RAS
NC
NC
UDQM
A9
4
A1
A4
A6
A7
NC
NC
LDQM
A10
5
A2
CKE
DQ1
DQ3
DQ4
DQ5
/WE
A11
6
/CAS
DQ0
DQ2
VDDQ
VSSQ
DQ6
DQ7
NC
A
0.75
B
C
D
E
F
G
H
6
5
4
3
2
1
0.30 0.05
8 0.1
0.23 0.05
1.0max
5.25
[Top View]
[Bottom View]
Note:
1. All Dimensions in millimeters
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
N16D1633LPA
NanoAmp Solutions, Inc.
Figure 3: Package Configuration (50-Pin TSOP II)
Advance Information
11.76 ± 0.20
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 Pin
TSOP II
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
DQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
0.80 BSC
20.95 ± 0.10
0.49
0.27
1.03 MAX
10.16 ± 0.10
[Top View]
0.80 NOM
1.20 MAX
1.00 ± 0.05
0.17 NOM
0
o
- 8
o
0.15
0.05
0.50 ± 0.10
NOTES:
1. All dimensions in millimeters unless otherwise noted
2. BSC = Basic lead spacing between centers
3. MAX / MIN
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
N16D1633LPA
NanoAmp Solutions, Inc.
Advance Information
Table 2: Pin Descriptions
PIN
CLK
CKE
/CS
A11
A0~A10
PIN NAME
System Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTIONS
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of the CLK
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend
or self refresh.
Enable or disable all inputs except CLK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0~RA10
Column Address: CA0~CA7
Auto Precharge : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in
write mode
Multiplexed data input/output pin
Power supply for internal circuits and input buffers
Power Supply for output buffers
No Connection
/RAS, /CAS, /WE
LDQM/UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
PCB设计
