N16D1633LPA
512K
x
16Bits
x
2Banks Low Power Synchronous DRAM
Description
These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These
products are offering fully synchronous operation and are
and output voltage levels are compatible with LVCMOS.
referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
Features
JEDEC standard 3.0V/3.3V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVCMOS interface.
• 4K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode.
• All inputs and outputs referenced to the positive edge of the
system clock.
• Data mask function by DQM.
• Internal dual banks operation.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Table1: Ordering Information
Part No.
N16D1633LPAC2-60I
N16D1633LPAC2-75I
N16D1633LPAC2-10I
N16D1633LPAT2-60I
N16D1633LPAT2-75I
N16D1633LPAT2-10I
Clock Freq.
166 MHz
133 MHz
100 MHz
166 MHz
133 MHz
100 MHz
Temperature
VDD/VDDQ
Interface
Package
60-Ball Green
FBGA
-25°C to 85°C
3.0V/3.0V
or
3.3V/3.3V
LVCMOS
50-Pin Green
TSOPII
Ver. A
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N16D1633LPA
Figure1: 60Ball FBGA Ball Assignment
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
2
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
3
4
5
6
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
NC
LDQM
/RAS
NC
NC
A0
A2
A3
7
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
/WE
/CAS
/CS
NC
A10
A1
VDD
[Top View]
Ver. A
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Figure2: 50Pin TSOPII Pin Assignment
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
BA
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
50 Pin
TSOP II
[Top View]
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Table2: Pin Descriptions
Pin
CLK
Pin Name
System Clock
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA7
: A10
CKE
/CS
A11
Clock Enable
Chip Select
Bank Address
A0~A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
/RAS, /CAS, /WE
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
LDQM/UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Ver. A
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Figure3: Functional Block Diagram
EXTENDED
MODE
REGISTER
CLOCK
GENERATOR
TCSR
PASR
CLK
CKE
ADDRESS
ROW
MODE
REGISTER
ADDRESS
BUFFER &
REFRESH
COUNTER
BANK B
BANK A
ROW DECODER
ROW DECODER
SENSE AMPLIFIER
/CS
/RAS
/CAS
/WE
COLUMN DECODER
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
COMMAND DECODER
CONTROL LOGIC
& LATCH CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
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